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Differential D93574

[RISCV] Define the vand, vor and vxor intrinsics
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Authored by evandro on Dec 18 2020, 6:47 PM.

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rGed73a78924a8: [RISCV] Define the vand, vor and vxor RVV intrinsics
Summary

Define the vand, vor and vxor IR intrinsics for the respective V instructions.




Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>

Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com>
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evandro created this revision.Dec 18 2020, 6:47 PM
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craig.topper accepted this revision.Dec 18 2020, 8:40 PM
LGTM
This revision is now accepted and ready to land.Dec 18 2020, 8:40 PM
frasercrmck accepted this revision.Dec 21 2020, 2:41 AM
LGTM
Closed by commit rGed73a78924a8: [RISCV] Define the vand, vor and vxor RVV intrinsics (authored by evandro).  ·  Explain WhyDec 21 2020, 2:21 PM
This revision was automatically updated to reflect the committed changes.
evandro added a commit: rGed73a78924a8: [RISCV] Define the vand, vor and vxor RVV intrinsics.
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Revision Contents
PathSize
llvm/
include/
llvm/
IR/
4 lines
lib/
Target/
RISCV/
14 lines
test/
CodeGen/
RISCV/
rvv/
1945 lines
2377 lines
1945 lines
2377 lines
1945 lines
2377 lines
Diff 312911
llvm/include/llvm/IR/IntrinsicsRISCV.td
Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {

  defm vadc : RISCVBinaryWithV0;
  defm vadc : RISCVBinaryWithV0;

  defm vmadc_carry_in : RISCVBinaryMaskOutWithV0;
  defm vmadc_carry_in : RISCVBinaryMaskOutWithV0;

  defm vmadc : RISCVBinaryMaskOut;
  defm vmadc : RISCVBinaryMaskOut;




  defm vsbc : RISCVBinaryWithV0;
  defm vsbc : RISCVBinaryWithV0;

  defm vmsbc_borrow_in : RISCVBinaryMaskOutWithV0;
  defm vmsbc_borrow_in : RISCVBinaryMaskOutWithV0;

  defm vmsbc : RISCVBinaryMaskOut;
  defm vmsbc : RISCVBinaryMaskOut;




  defm vand : RISCVBinaryAAX;

  defm vor : RISCVBinaryAAX;

  defm vxor : RISCVBinaryAAX;



  defm vsll : RISCVBinaryAAX;
  defm vsll : RISCVBinaryAAX;

  defm vsrl : RISCVBinaryAAX;
  defm vsrl : RISCVBinaryAAX;

  defm vsra : RISCVBinaryAAX;
  defm vsra : RISCVBinaryAAX;




  defm vnsrl : RISCVBinaryABX;
  defm vnsrl : RISCVBinaryABX;

  defm vnsra : RISCVBinaryABX;
  defm vnsra : RISCVBinaryABX;




  defm vminu : RISCVBinaryAAX;
  defm vminu : RISCVBinaryAAX;

Show All 27 Lines
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Show First 20 Lines • Show All 1,246 Lines • ▼ Show 20 Lines
defm PseudoVMADC       : VPseudoBinaryM_VM_XM_IM<"@earlyclobber $rd">;
defm PseudoVMADC       : VPseudoBinaryM_VM_XM_IM<"@earlyclobber $rd">;

defm PseudoVMADC       : VPseudoBinaryM_V_X_I<"@earlyclobber $rd">;
defm PseudoVMADC       : VPseudoBinaryM_V_X_I<"@earlyclobber $rd">;




defm PseudoVSBC        : VPseudoBinaryV_VM_XM;
defm PseudoVSBC        : VPseudoBinaryV_VM_XM;

defm PseudoVMSBC       : VPseudoBinaryM_VM_XM<"@earlyclobber $rd">;
defm PseudoVMSBC       : VPseudoBinaryM_VM_XM<"@earlyclobber $rd">;

defm PseudoVMSBC       : VPseudoBinaryM_V_X<"@earlyclobber $rd">;
defm PseudoVMSBC       : VPseudoBinaryM_V_X<"@earlyclobber $rd">;




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// 12.5. Vector Bitwise Logical Instructions

//===----------------------------------------------------------------------===//

defm PseudoVAND        : VPseudoBinaryV_VV_VX_VI;

defm PseudoVOR         : VPseudoBinaryV_VV_VX_VI;

defm PseudoVXOR        : VPseudoBinaryV_VV_VX_VI;



//===----------------------------------------------------------------------===//

// 12.6. Vector Single-Width Bit Shift Instructions
// 12.6. Vector Single-Width Bit Shift Instructions

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

defm PseudoVSLL        : VPseudoBinaryV_VV_VX_VI<uimm5>;
defm PseudoVSLL        : VPseudoBinaryV_VV_VX_VI<uimm5>;

defm PseudoVSRL        : VPseudoBinaryV_VV_VX_VI<uimm5>;
defm PseudoVSRL        : VPseudoBinaryV_VV_VX_VI<uimm5>;

defm PseudoVSRA        : VPseudoBinaryV_VV_VX_VI<uimm5>;
defm PseudoVSRA        : VPseudoBinaryV_VV_VX_VI<uimm5>;




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// 12.7. Vector Narrowing Integer Right Shift Instructions
// 12.7. Vector Narrowing Integer Right Shift Instructions

▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
defm "" : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">;
defm "" : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">;

defm "" : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">;
defm "" : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">;




defm "" : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">;
defm "" : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">;

defm "" : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">;
defm "" : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">;

defm "" : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">;
defm "" : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">;




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// 12.5. Vector Bitwise Logical Instructions

//===----------------------------------------------------------------------===//

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vand", "PseudoVAND", AllIntegerVectors>;

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vor", "PseudoVOR", AllIntegerVectors>;

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vxor", "PseudoVXOR", AllIntegerVectors>;



//===----------------------------------------------------------------------===//

// 12.6. Vector Single-Width Bit Shift Instructions
// 12.6. Vector Single-Width Bit Shift Instructions

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors,
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors,

                               uimm5>;
                               uimm5>;

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,

                               uimm5>;
                               uimm5>;

defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,

                               uimm5>;
                               uimm5>;

▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines
llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i32);



define <vscale x 1 x i8> @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i32);



define <vscale x 2 x i8> @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i32);



define <vscale x 4 x i8> @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i32);



define <vscale x 8 x i8> @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i32);



define <vscale x 16 x i8> @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i32);



define <vscale x 32 x i8> @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i32);



define <vscale x 64 x i8> @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i32);



define <vscale x 1 x i16> @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i32);



define <vscale x 2 x i16> @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i32);



define <vscale x 4 x i16> @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i32);



define <vscale x 8 x i16> @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i32);



define <vscale x 16 x i16> @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i32);



define <vscale x 32 x i16> @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32);



define <vscale x 1 x i32> @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32);



define <vscale x 2 x i32> @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32);



define <vscale x 4 x i32> @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32);



define <vscale x 8 x i32> @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32);



define <vscale x 16 x i32> @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i32);



define <vscale x 1 x i8> @intrinsic_vand_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i32);



define <vscale x 2 x i8> @intrinsic_vand_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i32);



define <vscale x 4 x i8> @intrinsic_vand_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i32);



define <vscale x 8 x i8> @intrinsic_vand_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i32);



define <vscale x 16 x i8> @intrinsic_vand_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i32);



define <vscale x 32 x i8> @intrinsic_vand_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i32);



define <vscale x 64 x i8> @intrinsic_vand_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i32);



define <vscale x 1 x i16> @intrinsic_vand_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i32);



define <vscale x 2 x i16> @intrinsic_vand_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i32);



define <vscale x 4 x i16> @intrinsic_vand_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i32);



define <vscale x 8 x i16> @intrinsic_vand_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i32);



define <vscale x 16 x i16> @intrinsic_vand_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i32);



define <vscale x 32 x i16> @intrinsic_vand_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i32);



define <vscale x 1 x i32> @intrinsic_vand_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i32);



define <vscale x 2 x i32> @intrinsic_vand_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i32);



define <vscale x 4 x i32> @intrinsic_vand_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i32);



define <vscale x 8 x i32> @intrinsic_vand_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i32);



define <vscale x 16 x i32> @intrinsic_vand_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i8> @intrinsic_vand_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vand_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vand_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vand_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vand_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vand_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vand_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i32 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vand_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vand_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vand_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vand_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vand_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vand_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vand_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vand_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vand_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vand_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vand_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i32> %a

}

llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i64);



define <vscale x 1 x i8> @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i64);



define <vscale x 2 x i8> @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i64);



define <vscale x 4 x i8> @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i64);



define <vscale x 8 x i8> @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i64);



define <vscale x 16 x i8> @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i64);



define <vscale x 32 x i8> @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i64);



define <vscale x 64 x i8> @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i64);



define <vscale x 1 x i16> @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i64);



define <vscale x 2 x i16> @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i64);



define <vscale x 4 x i16> @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i64);



define <vscale x 8 x i16> @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i64);



define <vscale x 16 x i16> @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i64);



define <vscale x 32 x i16> @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i64);



define <vscale x 1 x i32> @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i64);



define <vscale x 2 x i32> @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i64);



define <vscale x 4 x i32> @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i64);



define <vscale x 8 x i32> @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i64);



define <vscale x 16 x i32> @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64);



define <vscale x 1 x i64> @intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    <vscale x 1 x i64> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64);



define <vscale x 2 x i64> @intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    <vscale x 2 x i64> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64);



define <vscale x 4 x i64> @intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    <vscale x 4 x i64> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64);



define <vscale x 8 x i64> @intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    <vscale x 8 x i64> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i64);



define <vscale x 1 x i8> @intrinsic_vand_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i64);



define <vscale x 2 x i8> @intrinsic_vand_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i64);



define <vscale x 4 x i8> @intrinsic_vand_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i64);



define <vscale x 8 x i8> @intrinsic_vand_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i64);



define <vscale x 16 x i8> @intrinsic_vand_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i64);



define <vscale x 32 x i8> @intrinsic_vand_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i64);



define <vscale x 64 x i8> @intrinsic_vand_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i64);



define <vscale x 1 x i16> @intrinsic_vand_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i64);



define <vscale x 2 x i16> @intrinsic_vand_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i64);



define <vscale x 4 x i16> @intrinsic_vand_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i64);



define <vscale x 8 x i16> @intrinsic_vand_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i64);



define <vscale x 16 x i16> @intrinsic_vand_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i64);



define <vscale x 32 x i16> @intrinsic_vand_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i64);



define <vscale x 1 x i32> @intrinsic_vand_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i64);



define <vscale x 2 x i32> @intrinsic_vand_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i64);



define <vscale x 4 x i32> @intrinsic_vand_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i64);



define <vscale x 8 x i32> @intrinsic_vand_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i64);



define <vscale x 16 x i32> @intrinsic_vand_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(

  <vscale x 1 x i64>,

  i64,

  i64);



define <vscale x 1 x i64> @intrinsic_vand_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(

  <vscale x 2 x i64>,

  i64,

  i64);



define <vscale x 2 x i64> @intrinsic_vand_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(

  <vscale x 4 x i64>,

  i64,

  i64);



define <vscale x 4 x i64> @intrinsic_vand_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(

  <vscale x 8 x i64>,

  i64,

  i64);



define <vscale x 8 x i64> @intrinsic_vand_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



define <vscale x 1 x i8> @intrinsic_vand_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vand_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vand_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vand_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vand_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vand_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vand_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i64 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vand_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vand_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vand_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vand_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vand_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vand_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vand_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vand_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vand_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vand_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vand_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i64> @intrinsic_vand_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 1 x i64> %a

}



define <vscale x 1 x i64> @intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vand_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 2 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vand_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 4 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vand_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 8 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i64> %a

}

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i32);



define <vscale x 1 x i8> @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i32);



define <vscale x 2 x i8> @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i32);



define <vscale x 4 x i8> @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i32);



define <vscale x 8 x i8> @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i32);



define <vscale x 16 x i8> @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i32);



define <vscale x 32 x i8> @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i32);



define <vscale x 64 x i8> @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i32);



define <vscale x 1 x i16> @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i32);



define <vscale x 2 x i16> @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i32);



define <vscale x 4 x i16> @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i32);



define <vscale x 8 x i16> @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i32);



define <vscale x 16 x i16> @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i32);



define <vscale x 32 x i16> @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32);



define <vscale x 1 x i32> @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32);



define <vscale x 2 x i32> @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32);



define <vscale x 4 x i32> @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32);



define <vscale x 8 x i32> @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32);



define <vscale x 16 x i32> @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i32);



define <vscale x 1 x i8> @intrinsic_vor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i32);



define <vscale x 2 x i8> @intrinsic_vor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i32);



define <vscale x 4 x i8> @intrinsic_vor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i32);



define <vscale x 8 x i8> @intrinsic_vor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i32);



define <vscale x 16 x i8> @intrinsic_vor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i32);



define <vscale x 32 x i8> @intrinsic_vor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i32);



define <vscale x 64 x i8> @intrinsic_vor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i32);



define <vscale x 1 x i16> @intrinsic_vor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i32);



define <vscale x 2 x i16> @intrinsic_vor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i32);



define <vscale x 4 x i16> @intrinsic_vor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i32);



define <vscale x 8 x i16> @intrinsic_vor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i32);



define <vscale x 16 x i16> @intrinsic_vor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i32);



define <vscale x 32 x i16> @intrinsic_vor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i32);



define <vscale x 1 x i32> @intrinsic_vor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i32);



define <vscale x 2 x i32> @intrinsic_vor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i32);



define <vscale x 4 x i32> @intrinsic_vor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i32);



define <vscale x 8 x i32> @intrinsic_vor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i32);



define <vscale x 16 x i32> @intrinsic_vor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i8> @intrinsic_vor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i32 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i32> %a

}

llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i64);



define <vscale x 1 x i8> @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i64);



define <vscale x 2 x i8> @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i64);



define <vscale x 4 x i8> @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i64);



define <vscale x 8 x i8> @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i64);



define <vscale x 16 x i8> @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i64);



define <vscale x 32 x i8> @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i64);



define <vscale x 64 x i8> @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i64);



define <vscale x 1 x i16> @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i64);



define <vscale x 2 x i16> @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i64);



define <vscale x 4 x i16> @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i64);



define <vscale x 8 x i16> @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i64);



define <vscale x 16 x i16> @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i64);



define <vscale x 32 x i16> @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i64);



define <vscale x 1 x i32> @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i64);



define <vscale x 2 x i32> @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i64);



define <vscale x 4 x i32> @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i64);



define <vscale x 8 x i32> @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i64);



define <vscale x 16 x i32> @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64);



define <vscale x 1 x i64> @intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    <vscale x 1 x i64> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64);



define <vscale x 2 x i64> @intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    <vscale x 2 x i64> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64);



define <vscale x 4 x i64> @intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    <vscale x 4 x i64> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64);



define <vscale x 8 x i64> @intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    <vscale x 8 x i64> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i64);



define <vscale x 1 x i8> @intrinsic_vor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i64);



define <vscale x 2 x i8> @intrinsic_vor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i64);



define <vscale x 4 x i8> @intrinsic_vor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i64);



define <vscale x 8 x i8> @intrinsic_vor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i64);



define <vscale x 16 x i8> @intrinsic_vor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i64);



define <vscale x 32 x i8> @intrinsic_vor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i64);



define <vscale x 64 x i8> @intrinsic_vor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i64);



define <vscale x 1 x i16> @intrinsic_vor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i64);



define <vscale x 2 x i16> @intrinsic_vor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i64);



define <vscale x 4 x i16> @intrinsic_vor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i64);



define <vscale x 8 x i16> @intrinsic_vor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i64);



define <vscale x 16 x i16> @intrinsic_vor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i64);



define <vscale x 32 x i16> @intrinsic_vor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i64);



define <vscale x 1 x i32> @intrinsic_vor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i64);



define <vscale x 2 x i32> @intrinsic_vor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i64);



define <vscale x 4 x i32> @intrinsic_vor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i64);



define <vscale x 8 x i32> @intrinsic_vor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i64);



define <vscale x 16 x i32> @intrinsic_vor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(

  <vscale x 1 x i64>,

  i64,

  i64);



define <vscale x 1 x i64> @intrinsic_vor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(

  <vscale x 2 x i64>,

  i64,

  i64);



define <vscale x 2 x i64> @intrinsic_vor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(

  <vscale x 4 x i64>,

  i64,

  i64);



define <vscale x 4 x i64> @intrinsic_vor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(

  <vscale x 8 x i64>,

  i64,

  i64);



define <vscale x 8 x i64> @intrinsic_vor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



define <vscale x 1 x i8> @intrinsic_vor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i64 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i64> @intrinsic_vor_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 1 x i64> %a

}



define <vscale x 1 x i64> @intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vor_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 2 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vor_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 4 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vor_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 8 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i64> %a

}

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i32);



define <vscale x 1 x i8> @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i32);



define <vscale x 2 x i8> @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i32);



define <vscale x 4 x i8> @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i32);



define <vscale x 8 x i8> @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i32);



define <vscale x 16 x i8> @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i32);



define <vscale x 32 x i8> @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i32);



define <vscale x 64 x i8> @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i32);



define <vscale x 1 x i16> @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i32);



define <vscale x 2 x i16> @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i32);



define <vscale x 4 x i16> @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i32);



define <vscale x 8 x i16> @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i32);



define <vscale x 16 x i16> @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i32);



define <vscale x 32 x i16> @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32);



define <vscale x 1 x i32> @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32);



define <vscale x 2 x i32> @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32);



define <vscale x 4 x i32> @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32);



define <vscale x 8 x i32> @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32);



define <vscale x 16 x i32> @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i32);



define <vscale x 1 x i8> @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i8> @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i32);



define <vscale x 2 x i8> @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i8> @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i32);



define <vscale x 4 x i8> @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i8> @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i32);



define <vscale x 8 x i8> @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i8> @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i32);



define <vscale x 16 x i8> @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i8> @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i32);



define <vscale x 32 x i8> @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i8> @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i32);



define <vscale x 64 x i8> @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i32 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i32);



define <vscale x 64 x i8> @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i32 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i32);



define <vscale x 1 x i16> @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i16> @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i32);



define <vscale x 2 x i16> @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i16> @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i32);



define <vscale x 4 x i16> @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i16> @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i32);



define <vscale x 8 x i16> @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i16> @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i32);



define <vscale x 16 x i16> @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i16> @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i32);



define <vscale x 32 x i16> @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i32 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i32);



define <vscale x 32 x i16> @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i32 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i32);



define <vscale x 1 x i32> @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i32);



define <vscale x 1 x i32> @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i32 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i32);



define <vscale x 2 x i32> @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i32);



define <vscale x 2 x i32> @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i32 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i32);



define <vscale x 4 x i32> @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i32);



define <vscale x 4 x i32> @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i32 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i32);



define <vscale x 8 x i32> @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i32);



define <vscale x 8 x i32> @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i32 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i32);



define <vscale x 16 x i32> @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i32 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i32);



define <vscale x 16 x i32> @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i32 %4)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i8> @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i32 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i32 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i32 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i32 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i32 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i32 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i32 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i32 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i32 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i32 %3)



  ret <vscale x 16 x i32> %a

}

llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \

; RUN:   --riscv-no-aliases < %s | FileCheck %s

declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i64);



define <vscale x 1 x i8> @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    <vscale x 1 x i8> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i64);



define <vscale x 2 x i8> @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    <vscale x 2 x i8> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i64);



define <vscale x 4 x i8> @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    <vscale x 4 x i8> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i64);



define <vscale x 8 x i8> @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    <vscale x 8 x i8> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i64);



define <vscale x 16 x i8> @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    <vscale x 16 x i8> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i64);



define <vscale x 32 x i8> @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    <vscale x 32 x i8> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i64);



define <vscale x 64 x i8> @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    <vscale x 64 x i8> %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i64);



define <vscale x 1 x i16> @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    <vscale x 1 x i16> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i64);



define <vscale x 2 x i16> @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    <vscale x 2 x i16> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i64);



define <vscale x 4 x i16> @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    <vscale x 4 x i16> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i64);



define <vscale x 8 x i16> @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    <vscale x 8 x i16> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i64);



define <vscale x 16 x i16> @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    <vscale x 16 x i16> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i64);



define <vscale x 32 x i16> @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    <vscale x 32 x i16> %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i64);



define <vscale x 1 x i32> @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    <vscale x 1 x i32> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i64);



define <vscale x 2 x i32> @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    <vscale x 2 x i32> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i64);



define <vscale x 4 x i32> @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    <vscale x 4 x i32> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i64);



define <vscale x 8 x i32> @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    <vscale x 8 x i32> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i64);



define <vscale x 16 x i32> @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    <vscale x 16 x i32> %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64);



define <vscale x 1 x i64> @intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.nxv1i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.nxv1i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    <vscale x 1 x i64> %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64);



define <vscale x 2 x i64> @intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.nxv2i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.nxv2i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    <vscale x 2 x i64> %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64);



define <vscale x 4 x i64> @intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.nxv4i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.nxv4i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    <vscale x 4 x i64> %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64);



define <vscale x 8 x i64> @intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    <vscale x 8 x i64> %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

  <vscale x 1 x i8>,

  i8,

  i64);



define <vscale x 1 x i8> @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

  <vscale x 1 x i8>,

  <vscale x 1 x i8>,

  i8,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i8> @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

  <vscale x 2 x i8>,

  i8,

  i64);



define <vscale x 2 x i8> @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

  <vscale x 2 x i8>,

  <vscale x 2 x i8>,

  i8,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i8> @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

  <vscale x 4 x i8>,

  i8,

  i64);



define <vscale x 4 x i8> @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

  <vscale x 4 x i8>,

  <vscale x 4 x i8>,

  i8,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i8> @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

  <vscale x 8 x i8>,

  i8,

  i64);



define <vscale x 8 x i8> @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

  <vscale x 8 x i8>,

  <vscale x 8 x i8>,

  i8,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i8> @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

  <vscale x 16 x i8>,

  i8,

  i64);



define <vscale x 16 x i8> @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

  <vscale x 16 x i8>,

  <vscale x 16 x i8>,

  i8,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i8> @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

  <vscale x 32 x i8>,

  i8,

  i64);



define <vscale x 32 x i8> @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

  <vscale x 32 x i8>,

  <vscale x 32 x i8>,

  i8,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i8> @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

  <vscale x 64 x i8>,

  i8,

  i64);



define <vscale x 64 x i8> @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 %1,

    i64 %2)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

  <vscale x 64 x i8>,

  <vscale x 64 x i8>,

  i8,

  <vscale x 64 x i1>,

  i64);



define <vscale x 64 x i8> @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 %2,

    <vscale x 64 x i1> %3,

    i64 %4)



  ret <vscale x 64 x i8> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

  <vscale x 1 x i16>,

  i16,

  i64);



define <vscale x 1 x i16> @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

  <vscale x 1 x i16>,

  <vscale x 1 x i16>,

  i16,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i16> @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

  <vscale x 2 x i16>,

  i16,

  i64);



define <vscale x 2 x i16> @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

  <vscale x 2 x i16>,

  <vscale x 2 x i16>,

  i16,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i16> @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

  <vscale x 4 x i16>,

  i16,

  i64);



define <vscale x 4 x i16> @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

  <vscale x 4 x i16>,

  <vscale x 4 x i16>,

  i16,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i16> @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

  <vscale x 8 x i16>,

  i16,

  i64);



define <vscale x 8 x i16> @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

  <vscale x 8 x i16>,

  <vscale x 8 x i16>,

  i16,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i16> @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

  <vscale x 16 x i16>,

  i16,

  i64);



define <vscale x 16 x i16> @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

  <vscale x 16 x i16>,

  <vscale x 16 x i16>,

  i16,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i16> @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

  <vscale x 32 x i16>,

  i16,

  i64);



define <vscale x 32 x i16> @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 %1,

    i64 %2)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

  <vscale x 32 x i16>,

  <vscale x 32 x i16>,

  i16,

  <vscale x 32 x i1>,

  i64);



define <vscale x 32 x i16> @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 %2,

    <vscale x 32 x i1> %3,

    i64 %4)



  ret <vscale x 32 x i16> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

  <vscale x 1 x i32>,

  i32,

  i64);



define <vscale x 1 x i32> @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

  <vscale x 1 x i32>,

  <vscale x 1 x i32>,

  i32,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i32> @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

  <vscale x 2 x i32>,

  i32,

  i64);



define <vscale x 2 x i32> @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

  <vscale x 2 x i32>,

  <vscale x 2 x i32>,

  i32,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i32> @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

  <vscale x 4 x i32>,

  i32,

  i64);



define <vscale x 4 x i32> @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

  <vscale x 4 x i32>,

  <vscale x 4 x i32>,

  i32,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i32> @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

  <vscale x 8 x i32>,

  i32,

  i64);



define <vscale x 8 x i32> @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

  <vscale x 8 x i32>,

  <vscale x 8 x i32>,

  i32,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i32> @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

  <vscale x 16 x i32>,

  i32,

  i64);



define <vscale x 16 x i32> @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 %1,

    i64 %2)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

  <vscale x 16 x i32>,

  <vscale x 16 x i32>,

  i32,

  <vscale x 16 x i1>,

  i64);



define <vscale x 16 x i32> @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 %2,

    <vscale x 16 x i1> %3,

    i64 %4)



  ret <vscale x 16 x i32> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(

  <vscale x 1 x i64>,

  i64,

  i64);



define <vscale x 1 x i64> @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(

  <vscale x 1 x i64>,

  <vscale x 1 x i64>,

  i64,

  <vscale x 1 x i1>,

  i64);



define <vscale x 1 x i64> @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 %2,

    <vscale x 1 x i1> %3,

    i64 %4)



  ret <vscale x 1 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(

  <vscale x 2 x i64>,

  i64,

  i64);



define <vscale x 2 x i64> @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(

  <vscale x 2 x i64>,

  <vscale x 2 x i64>,

  i64,

  <vscale x 2 x i1>,

  i64);



define <vscale x 2 x i64> @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 %2,

    <vscale x 2 x i1> %3,

    i64 %4)



  ret <vscale x 2 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(

  <vscale x 4 x i64>,

  i64,

  i64);



define <vscale x 4 x i64> @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(

  <vscale x 4 x i64>,

  <vscale x 4 x i64>,

  i64,

  <vscale x 4 x i1>,

  i64);



define <vscale x 4 x i64> @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 %2,

    <vscale x 4 x i1> %3,

    i64 %4)



  ret <vscale x 4 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(

  <vscale x 8 x i64>,

  i64,

  i64);



define <vscale x 8 x i64> @intrinsic_vxor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 %1,

    i64 %2)



  ret <vscale x 8 x i64> %a

}



declare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(

  <vscale x 8 x i64>,

  <vscale x 8 x i64>,

  i64,

  <vscale x 8 x i1>,

  i64);



define <vscale x 8 x i64> @intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 %2,

    <vscale x 8 x i1> %3,

    i64 %4)



  ret <vscale x 8 x i64> %a

}



define <vscale x 1 x i8> @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 1 x i8> %a

}



define <vscale x 1 x i8> @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(

    <vscale x 1 x i8> %0,

    <vscale x 1 x i8> %1,

    i8 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 2 x i8> %a

}



define <vscale x 2 x i8> @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(

    <vscale x 2 x i8> %0,

    <vscale x 2 x i8> %1,

    i8 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 4 x i8> %a

}



define <vscale x 4 x i8> @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(

    <vscale x 4 x i8> %0,

    <vscale x 4 x i8> %1,

    i8 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 8 x i8> %a

}



define <vscale x 8 x i8> @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(

    <vscale x 8 x i8> %0,

    <vscale x 8 x i8> %1,

    i8 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 16 x i8> %a

}



define <vscale x 16 x i8> @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(

    <vscale x 16 x i8> %0,

    <vscale x 16 x i8> %1,

    i8 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 32 x i8> %a

}



define <vscale x 32 x i8> @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(

    <vscale x 32 x i8> %0,

    <vscale x 32 x i8> %1,

    i8 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    i8 9,

    i64 %1)



  ret <vscale x 64 x i8> %a

}



define <vscale x 64 x i8> @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(

    <vscale x 64 x i8> %0,

    <vscale x 64 x i8> %1,

    i8 9,

    <vscale x 64 x i1> %2,

    i64 %3)



  ret <vscale x 64 x i8> %a

}



define <vscale x 1 x i16> @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 1 x i16> %a

}



define <vscale x 1 x i16> @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(

    <vscale x 1 x i16> %0,

    <vscale x 1 x i16> %1,

    i16 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 2 x i16> %a

}



define <vscale x 2 x i16> @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(

    <vscale x 2 x i16> %0,

    <vscale x 2 x i16> %1,

    i16 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 4 x i16> %a

}



define <vscale x 4 x i16> @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(

    <vscale x 4 x i16> %0,

    <vscale x 4 x i16> %1,

    i16 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 8 x i16> %a

}



define <vscale x 8 x i16> @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(

    <vscale x 8 x i16> %0,

    <vscale x 8 x i16> %1,

    i16 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 16 x i16> %a

}



define <vscale x 16 x i16> @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(

    <vscale x 16 x i16> %0,

    <vscale x 16 x i16> %1,

    i16 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    i16 9,

    i64 %1)



  ret <vscale x 32 x i16> %a

}



define <vscale x 32 x i16> @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(

    <vscale x 32 x i16> %0,

    <vscale x 32 x i16> %1,

    i16 9,

    <vscale x 32 x i1> %2,

    i64 %3)



  ret <vscale x 32 x i16> %a

}



define <vscale x 1 x i32> @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 1 x i32> %a

}



define <vscale x 1 x i32> @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(

    <vscale x 1 x i32> %0,

    <vscale x 1 x i32> %1,

    i32 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 2 x i32> %a

}



define <vscale x 2 x i32> @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(

    <vscale x 2 x i32> %0,

    <vscale x 2 x i32> %1,

    i32 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 4 x i32> %a

}



define <vscale x 4 x i32> @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(

    <vscale x 4 x i32> %0,

    <vscale x 4 x i32> %1,

    i32 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 8 x i32> %a

}



define <vscale x 8 x i32> @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(

    <vscale x 8 x i32> %0,

    <vscale x 8 x i32> %1,

    i32 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    i32 9,

    i64 %1)



  ret <vscale x 16 x i32> %a

}



define <vscale x 16 x i32> @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(

    <vscale x 16 x i32> %0,

    <vscale x 16 x i32> %1,

    i32 9,

    <vscale x 16 x i1> %2,

    i64 %3)



  ret <vscale x 16 x i32> %a

}



define <vscale x 1 x i64> @intrinsic_vxor_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 1 x i64> %a

}



define <vscale x 1 x i64> @intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(

    <vscale x 1 x i64> %0,

    <vscale x 1 x i64> %1,

    i64 9,

    <vscale x 1 x i1> %2,

    i64 %3)



  ret <vscale x 1 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vxor_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 2 x i64> %a

}



define <vscale x 2 x i64> @intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(

    <vscale x 2 x i64> %0,

    <vscale x 2 x i64> %1,

    i64 9,

    <vscale x 2 x i1> %2,

    i64 %3)



  ret <vscale x 2 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vxor_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 4 x i64> %a

}



define <vscale x 4 x i64> @intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(

    <vscale x 4 x i64> %0,

    <vscale x 4 x i64> %1,

    i64 9,

    <vscale x 4 x i1> %2,

    i64 %3)



  ret <vscale x 4 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vxor_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    i64 9,

    i64 %1)



  ret <vscale x 8 x i64> %a

}



define <vscale x 8 x i64> @intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {

entry:

; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64

; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu

; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t

  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(

    <vscale x 8 x i64> %0,

    <vscale x 8 x i64> %1,

    i64 9,

    <vscale x 8 x i1> %2,

    i64 %3)



  ret <vscale x 8 x i64> %a

}