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Differential D93218

[RISCV] Define vminu/vmin/vmaxu/vmax intrinsics.
ClosedPublic

Authored by HsiangKai on Dec 14 2020, 7:42 AM.

Details

Reviewers
craig.topper
evandro
luismarques
frasercrmck
rogfer01
Commits
rG903f2950091a: [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
Summary

Define vminu/vmin/vmaxu/vmax intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Diff Detail

Event Timeline

HsiangKai created this revision.Dec 14 2020, 7:42 AM
Herald added subscribers: NickHung, apazos, sameer.abuasal and 23 others. · View Herald TranscriptDec 14 2020, 7:42 AM
HsiangKai requested review of this revision.Dec 14 2020, 7:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 14 2020, 7:42 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B82279: Diff 311595.Dec 14 2020, 7:42 AM
HsiangKai added a parent revision: D93207: [RISCV] Define vnsrl/vnsra intrinsics..Dec 14 2020, 7:45 AM
craig.topper added a comment.Dec 14 2020, 1:21 PM

This seems like good to me

rogfer01 added a comment.EditedDec 14 2020, 11:59 PM

Agreed, these instructions and their intrinsics seems pretty uncontroversial. LGTM.

HsiangKai updated this revision to Diff 311822.Dec 15 2020, 12:32 AM
HsiangKai edited the summary of this revision. (Show Details)

Update test cases.

Harbormaster completed remote builds in B82416: Diff 311822.Dec 15 2020, 12:33 AM
frasercrmck added a comment.Dec 15 2020, 1:50 AM

LGTM

frasercrmck accepted this revision.Dec 15 2020, 1:50 AM
This revision is now accepted and ready to land.Dec 15 2020, 1:50 AM
This revision was landed with ongoing or failed builds.Dec 15 2020, 2:32 PM
Closed by commit rG903f2950091a: [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rG903f2950091a: [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics..

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
5 lines
lib/
Target/
RISCV/
16 lines
test/
CodeGen/
RISCV/
rvv/
1761 lines
1761 lines
1761 lines
1761 lines

Diff 311595

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vsll : RISCVBinaryAAX; defm vsll : RISCVBinaryAAX;
defm vsrl : RISCVBinaryAAX; defm vsrl : RISCVBinaryAAX;
defm vsra : RISCVBinaryAAX; defm vsra : RISCVBinaryAAX;
defm vnsrl : RISCVBinaryABX; defm vnsrl : RISCVBinaryABX;
defm vnsra : RISCVBinaryABX; defm vnsra : RISCVBinaryABX;
defm vminu : RISCVBinaryAAX;
defm vmin : RISCVBinaryAAX;
defm vmaxu : RISCVBinaryAAX;
defm vmax : RISCVBinaryAAX;
} // TargetPrefix = "riscv" } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVNSRL : VPseudoBinaryV_WV_WX_WI; defm PseudoVNSRL : VPseudoBinaryV_WV_WX_WI;
defm PseudoVNSRA : VPseudoBinaryV_WV_WX_WI; defm PseudoVNSRA : VPseudoBinaryV_WV_WX_WI;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.9. Vector Integer Min/Max Instructions
//===----------------------------------------------------------------------===//
defm PseudoVMINU : VPseudoBinaryV_VV_VX;
defm PseudoVMIN : VPseudoBinaryV_VV_VX;
defm PseudoVMAXU : VPseudoBinaryV_VV_VX;
defm PseudoVMAX : VPseudoBinaryV_VV_VX;
//===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Whole-register vector patterns. // Whole-register vector patterns.
defm "" : VPatBinarySDNode<add, "PseudoVADD">; defm "" : VPatBinarySDNode<add, "PseudoVADD">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12. Vector Integer Arithmetic Instructions // 12. Vector Integer Arithmetic Instructions
Show All 40 Linesdefm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
uimm5>; uimm5>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL">; defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL">;
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA">; defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA">;
//===----------------------------------------------------------------------===//
// 12.9. Vector Integer Min/Max Instructions
//===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX<"int_riscv_vminu", "PseudoVMINU", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmin", "PseudoVMIN", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmaxu", "PseudoVMAXU", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmax", "PseudoVMAX", AllIntegerVectors>;
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]

llvm/test/CodeGen/RISCV/rvv/vmax.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64);
define <vscale x 1 x i8> @intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmax.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmax.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i64);
define <vscale x 2 x i8> @intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmax.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmax.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i64);
define <vscale x 4 x i8> @intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmax.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmax.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i64);
define <vscale x 8 x i8> @intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i64);
define <vscale x 16 x i8> @intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmax.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmax.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmax.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i64);
define <vscale x 32 x i8> @intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmax.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmax.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmax.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmax.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i64);
define <vscale x 64 x i8> @intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmax.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
define <vscale x 1 x i16> @intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmax.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmax.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmax.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmax.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
define <vscale x 2 x i16> @intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmax.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmax.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmax.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmax.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
define <vscale x 4 x i16> @intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmax.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmax.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
define <vscale x 8 x i16> @intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmax.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmax.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmax.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmax.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
define <vscale x 16 x i16> @intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmax.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmax.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmax.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmax.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
define <vscale x 32 x i16> @intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmax.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define <vscale x 1 x i32> @intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmax.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmax.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmax.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmax.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i64);
define <vscale x 2 x i32> @intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmax.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i64);
define <vscale x 4 x i32> @intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmax.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmax.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmax.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i64);
define <vscale x 8 x i32> @intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmax.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmax.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmax.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmax.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i64);
define <vscale x 16 x i32> @intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64);
define <vscale x 1 x i64> @intrinsic_vmax_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmax_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64);
define <vscale x 2 x i64> @intrinsic_vmax_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmax_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64);
define <vscale x 4 x i64> @intrinsic_vmax_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmax_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64);
define <vscale x 8 x i64> @intrinsic_vmax_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vmax_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmax.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmax.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vmax_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmax.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmax.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vmax_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmax.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmax.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vmax_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmax.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmax.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vmax_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmax.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmax.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmax.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vmax_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmax.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmax.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmax.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmax.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vmax_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmax.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vmax_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmax.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmax.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmax.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmax.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vmax_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmax.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmax.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmax.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmax.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vmax_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmax.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmax.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmax.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmax.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vmax_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmax.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmax.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmax.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmax.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vmax_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmax.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmax.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmax.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmax.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vmax_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmax.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vmax_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmax.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmax.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmax.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmax.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vmax_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmax.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmax.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmax.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vmax_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmax.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmax.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmax.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vmax_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmax.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmax.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmax.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmax.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vmax_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vmax_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vmaxu.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64);
define <vscale x 1 x i8> @intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmaxu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmaxu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i64);
define <vscale x 2 x i8> @intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmaxu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmaxu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i64);
define <vscale x 4 x i8> @intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmaxu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmaxu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i64);
define <vscale x 8 x i8> @intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i64);
define <vscale x 16 x i8> @intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmaxu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmaxu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmaxu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i64);
define <vscale x 32 x i8> @intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmaxu.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmaxu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmaxu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmaxu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i64);
define <vscale x 64 x i8> @intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmaxu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
define <vscale x 1 x i16> @intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmaxu.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmaxu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmaxu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmaxu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
define <vscale x 2 x i16> @intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmaxu.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmaxu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmaxu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
define <vscale x 4 x i16> @intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmaxu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
define <vscale x 8 x i16> @intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmaxu.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmaxu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmaxu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmaxu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
define <vscale x 16 x i16> @intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmaxu.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmaxu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmaxu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmaxu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
define <vscale x 32 x i16> @intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmaxu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define <vscale x 1 x i32> @intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmaxu.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmaxu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmaxu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i64);
define <vscale x 2 x i32> @intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i64);
define <vscale x 4 x i32> @intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmaxu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmaxu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmaxu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i64);
define <vscale x 8 x i32> @intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmaxu.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmaxu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmaxu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmaxu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i64);
define <vscale x 16 x i32> @intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64);
define <vscale x 1 x i64> @intrinsic_vmaxu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmaxu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64);
define <vscale x 2 x i64> @intrinsic_vmaxu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmaxu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64);
define <vscale x 4 x i64> @intrinsic_vmaxu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmaxu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64);
define <vscale x 8 x i64> @intrinsic_vmaxu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmaxu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmaxu.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmaxu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmaxu.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmaxu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmaxu.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmaxu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmaxu.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmaxu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmaxu.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmaxu.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmaxu.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmaxu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmaxu.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmaxu.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmaxu.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmaxu.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmaxu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmaxu.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmaxu.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmaxu.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmaxu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmaxu.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmaxu.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmaxu.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmaxu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmaxu.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmaxu.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmaxu.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmaxu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmaxu.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmaxu.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmaxu.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmaxu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmaxu.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmaxu.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmaxu.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmaxu.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmaxu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmaxu.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmaxu.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmaxu.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmaxu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmaxu.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmaxu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmaxu.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmaxu.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmaxu.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmaxu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmaxu.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmaxu.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vmin.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64);
define <vscale x 1 x i8> @intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i64);
define <vscale x 2 x i8> @intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmin.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmin.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i64);
define <vscale x 4 x i8> @intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmin.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmin.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i64);
define <vscale x 8 x i8> @intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i64);
define <vscale x 16 x i8> @intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmin.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmin.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmin.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i64);
define <vscale x 32 x i8> @intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmin.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmin.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmin.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmin.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i64);
define <vscale x 64 x i8> @intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmin.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
define <vscale x 1 x i16> @intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmin.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmin.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmin.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmin.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
define <vscale x 2 x i16> @intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmin.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmin.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmin.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmin.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
define <vscale x 4 x i16> @intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmin.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmin.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
define <vscale x 8 x i16> @intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmin.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmin.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmin.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmin.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
define <vscale x 16 x i16> @intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmin.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmin.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmin.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmin.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
define <vscale x 32 x i16> @intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmin.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define <vscale x 1 x i32> @intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmin.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmin.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmin.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmin.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i64);
define <vscale x 2 x i32> @intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmin.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i64);
define <vscale x 4 x i32> @intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmin.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmin.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmin.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i64);
define <vscale x 8 x i32> @intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmin.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmin.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmin.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmin.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i64);
define <vscale x 16 x i32> @intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64);
define <vscale x 1 x i64> @intrinsic_vmin_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmin_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64);
define <vscale x 2 x i64> @intrinsic_vmin_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmin_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64);
define <vscale x 4 x i64> @intrinsic_vmin_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmin_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64);
define <vscale x 8 x i64> @intrinsic_vmin_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vmin_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vmin_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vmin.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vmin.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vmin_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vmin.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vmin.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vmin_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vmin.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vmin.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vmin_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vmin.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vmin.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmin.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vmin_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vmin.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vmin.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vmin.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmin.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vmin_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmin.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vmin_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vmin.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vmin.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vmin.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmin.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vmin_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vmin.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vmin.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vmin.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmin.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vmin_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vmin.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vmin.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vmin.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmin.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vmin_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vmin.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vmin.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vmin.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmin.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vmin_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vmin.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vmin.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vmin.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmin.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vmin_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmin.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vmin_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vmin.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vmin.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vmin.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmin.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vmin_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vmin.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vmin.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vmin.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vmin_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vmin.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vmin.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmin.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vmin_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vmin.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vmin.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vmin.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmin.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vmin_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vmin_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vminu.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64);
define <vscale x 1 x i8> @intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vminu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vminu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i64);
define <vscale x 2 x i8> @intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vminu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vminu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i64);
define <vscale x 4 x i8> @intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vminu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vminu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i64);
define <vscale x 8 x i8> @intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i64);
define <vscale x 16 x i8> @intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vminu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vminu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vminu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i64);
define <vscale x 32 x i8> @intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vminu.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vminu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vminu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vminu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i64);
define <vscale x 64 x i8> @intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vminu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
define <vscale x 1 x i16> @intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vminu.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vminu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vminu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vminu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
define <vscale x 2 x i16> @intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vminu.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vminu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vminu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vminu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
define <vscale x 4 x i16> @intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vminu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vminu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
define <vscale x 8 x i16> @intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vminu.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vminu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vminu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vminu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
define <vscale x 16 x i16> @intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vminu.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vminu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vminu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vminu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
define <vscale x 32 x i16> @intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vminu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define <vscale x 1 x i32> @intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vminu.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vminu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vminu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vminu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i64);
define <vscale x 2 x i32> @intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vminu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i64);
define <vscale x 4 x i32> @intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vminu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vminu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vminu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i64);
define <vscale x 8 x i32> @intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vminu.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vminu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vminu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vminu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i64);
define <vscale x 16 x i32> @intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64);
define <vscale x 1 x i64> @intrinsic_vminu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vminu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64);
define <vscale x 2 x i64> @intrinsic_vminu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vminu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64);
define <vscale x 4 x i64> @intrinsic_vminu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vminu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64);
define <vscale x 8 x i64> @intrinsic_vminu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vminu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vminu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vminu.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vminu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vminu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vminu.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vminu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vminu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vminu.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vminu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vminu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vminu.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vminu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vminu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vminu.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vminu.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vminu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vminu.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vminu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vminu.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vminu.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vminu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vminu.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vminu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vminu.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vminu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vminu.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vminu.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vminu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vminu.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vminu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vminu.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vminu.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vminu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vminu.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vminu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vminu.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vminu.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vminu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vminu.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vminu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vminu.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vminu.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vminu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vminu.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vminu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vminu.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vminu.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vminu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vminu.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vminu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vminu.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vminu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vminu.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vminu.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vminu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vminu.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vminu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vminu.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vminu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vminu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vminu.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vminu.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vminu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vminu.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vminu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vminu.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vminu.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vminu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vminu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}