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[AArch64] Add a GPR64x8 register class
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Authored by pratlucas on Nov 19 2020, 2:06 AM.

Details

Summary

This adds a GPR64x8 register class that will be needed as the data
operand to the LD64B/ST64B family of instructions in the v8.7-A
Accelerator Extension, which load or store a contiguous range of eight
x-regs. It has to be its own register class so that register allocation
will have visibility of the full set of registers actually read/written
by the instructions, which will be needed when we add intrinsics and/or
inline asm access to this piece of architecture.

Patch written by Simon Tatham.

Diff Detail

Unit TestsFailed

TimeTest
50 msx64 windows > LLVM.CodeGen/XCore::threads.ll
Script: -- : 'RUN: at line 1'; c:\ws\w16c2-1\llvm-project\premerge-checks\build\bin\llc.exe -march=xcore < C:\ws\w16c2-1\llvm-project\premerge-checks\llvm\test\CodeGen\XCore\threads.ll | c:\ws\w16c2-1\llvm-project\premerge-checks\build\bin\filecheck.exe C:\ws\w16c2-1\llvm-project\premerge-checks\llvm\test\CodeGen\XCore\threads.ll

Event Timeline

pratlucas created this revision.Nov 19 2020, 2:06 AM
pratlucas requested review of this revision.Nov 19 2020, 2:06 AM
This revision is now accepted and ready to land.Nov 19 2020, 5:23 AM
This revision was landed with ongoing or failed builds.Dec 17 2020, 5:45 AM
This revision was automatically updated to reflect the committed changes.