[RISCV] ELF attribute for Zfh extension.

[HsiangKai]

Summary

Add Zfh into ELF march attribute.

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2144

Having each X and Z extension hard-code its length is going to get ugly (and this doesn't match the code style for variable names). Instead I think we should be making good use of StringRef::consume_front.

llvm/test/MC/RISCV/attribute-with-insts.s

13

This changes the test; we're no longer checking whether D implies F but instead whether (D or Zfh) implies F.

[luismarques]

llvm/lib/Object/ELFObjectFile.cpp

335

Do we need to actually consume the prefix, or would using just startswith be fine?

[jrtc27]

llvm/lib/Object/ELFObjectFile.cpp

335

For now, startswith would work due to the drop_until below. However, consume_front matches the take_front above, and will be important when we want to start parsing version numbers.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2144

... ok but now we drop that many characters twice: once from consume_front and once from drop_front below.

[HsiangKai]

D94931 is more complete.

llvm/lib/Object/ELFObjectFile.cpp

while (!Arch.empty()) {
         LLVM_FALLTHROUGH;
       case 'e':
       case 'm':
       case 'a':
       case 'f':
       case 'c':
         Features.AddFeature(Arch.take_front());
         break;
+      case 'z':
+        if (Arch.consume_front("zfh")) {
+          Features.AddFeature("experimental-zfh");
+          Features.AddFeature("f"); // Zfh implies F extension.
+        }
+        break;
       }
 
       // FIXME: Handle version numbers.
       Arch = Arch.drop_until([](char c) { return c == '_' || c == '\0'; });
       Arch = Arch.drop_while([](char c) { return c == '_'; });
     }
   }
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::parseDirectiveAttribute() {
   } else {
     if (Parser.getTok().isNot(AsmToken::String))
       return Error(Parser.getTok().getLoc(), "expected string constant");
 
     StringValue = Parser.getTok().getStringContents();
     Parser.Lex();
   }
 
   if (Parser.parseToken(AsmToken::EndOfStatement,
                         "unexpected token in '.attribute' directive"))
     return true;
 
   if (Tag == RISCVAttrs::ARCH) {
     StringRef Arch = StringValue;
     if (Arch.consume_front("rv32"))
       clearFeatureBits(RISCV::Feature64Bit, "64bit");
     else if (Arch.consume_front("rv64"))
       setFeatureBits(RISCV::Feature64Bit, "64bit");
     else
       return Error(ValueExprLoc, "bad arch string " + Arch);
 
+    unsigned drop_char_num = 1;
     while (!Arch.empty()) {
       if (Arch[0] == 'i')
         clearFeatureBits(RISCV::FeatureRV32E, "e");
       else if (Arch[0] == 'e')
         setFeatureBits(RISCV::FeatureRV32E, "e");
       else if (Arch[0] == 'g') {
         clearFeatureBits(RISCV::FeatureRV32E, "e");
         setFeatureBits(RISCV::FeatureStdExtM, "m");
         setFeatureBits(RISCV::FeatureStdExtA, "a");
         setFeatureBits(RISCV::FeatureStdExtF, "f");
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'm')
         setFeatureBits(RISCV::FeatureStdExtM, "m");
       else if (Arch[0] == 'a')
         setFeatureBits(RISCV::FeatureStdExtA, "a");
       else if (Arch[0] == 'f')
         setFeatureBits(RISCV::FeatureStdExtF, "f");
       else if (Arch[0] == 'd') {
         setFeatureBits(RISCV::FeatureStdExtF, "f");
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'c') {
         setFeatureBits(RISCV::FeatureStdExtC, "c");
+      } else if (Arch.consume_front("zfh")) {
+        setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+        drop_char_num = 3;
       } else
         return Error(ValueExprLoc, "bad arch string " + Arch);
 
-      Arch = Arch.drop_front(1);
+      Arch = Arch.drop_front(drop_char_num);
       int major = 0;
       int minor = 0;
       Arch.consumeInteger(10, major);
       Arch.consume_front("p");
       Arch.consumeInteger(10, minor);
       if (major != 0 || minor != 0) {
         Arch = Arch.drop_until([](char c) { return c == '_' || c == '"'; });
         Arch = Arch.drop_while([](char c) { return c == '_'; });
       }
     }
   }
 
   if (IsIntegerValue)
     getTargetStreamer().emitAttribute(Tag, IntegerValue);
   else {
     if (Tag != RISCVAttrs::ARCH) {
       getTargetStreamer().emitTextAttribute(Tag, StringValue);
     } else {
       std::string formalArchStr = "rv32";
       if (getFeatureBits(RISCV::Feature64Bit))
         formalArchStr = "rv64";
       if (getFeatureBits(RISCV::FeatureRV32E))
         formalArchStr = (Twine(formalArchStr) + "e1p9").str();
       else
         formalArchStr = (Twine(formalArchStr) + "i2p0").str();
 
       if (getFeatureBits(RISCV::FeatureStdExtM))
         formalArchStr = (Twine(formalArchStr) + "_m2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtA))
         formalArchStr = (Twine(formalArchStr) + "_a2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtF))
         formalArchStr = (Twine(formalArchStr) + "_f2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtD))
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
+      if (getFeatureBits(RISCV::FeatureExtZfh))
+        formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtA))
     Arch += "_a2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtF))
     Arch += "_f2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtD))
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
+  if (STI.hasFeature(RISCV::FeatureExtZfh))
+    Arch += "_zfh0p1";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
                                                formatted_raw_ostream &OS)
     : RISCVTargetStreamer(S), OS(OS) {}

llvm/test/CodeGen/RISCV/attributes.ll

 ;; Generate ELF attributes from llc.
 
 ; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - \
+; RUN:   | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - \
+; RUN:   | FileCheck --check-prefix=RV64ZFH %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
+; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32i2p0_mafdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ima2p_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+
+.attribute arch, "rv32ima2p_fdczfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zfh0p1"

llvm/test/MC/RISCV/attribute-with-insts.s

 ## Test .attribute effects.
 ## We do not provide '-mattr=' and '.option rvc' and enable extensions through
 ## '.attribute arch'.
 
 # RUN: llvm-mc -triple riscv32 -filetype=obj %s \
 # RUN:   | llvm-objdump --triple=riscv32 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
 # RUN: llvm-mc -triple riscv64 -filetype=obj %s \
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0_zfh0p1"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
 
 # CHECK-INST: c.addi a3, -32
 c.addi a3, -32
 
 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
 fmadd.d f10, f11, f12, f13, dyn
 
 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
 fmadd.s f10, f11, f12, f13, dyn
 
+# CHECK-INST: fmadd.h fa0, fa1, fa2, fa3, dyn
+fmadd.h f10, f11, f12, f13, dyn
+
 # CHECK-INST: addi ra, sp, 2
 addi ra, sp, 2
 
 # CHECK-INST: mul a4, ra, s0
 mul a4, ra, s0
 
 # CHECK-INST: addw a2, a3, a4
 addw a2, a3, a4

llvm/test/MC/RISCV/attribute.s

 ## Test llvm-mc could handle .attribute correctly.
 
 # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
 # RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
 
 .attribute stack_align, 16
 # CHECK: attribute      4, 16
 
-.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0"
-# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_c2p0"
+.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0_zfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_c2p0_zfh0p1"
 
 .attribute unaligned_access, 0
 # CHECK: attribute      6, 0
 
 .attribute priv_spec, 2
 # CHECK: attribute      8, 2
 
 .attribute priv_spec_minor, 0
 # CHECK: attribute      10, 0
 
 .attribute priv_spec_revision, 0
 # CHECK: attribute      12, 0