[AArch64] Select PAC/PACGA for ptrauth.sign/sign_generic.

[ab]

Summary

This builds on D90868 to introduce the straightforward isel patterns for sign/sign_generic.

[danielkiss]

llvm/test/CodeGen/AArch64/ptrauth-intrinsics.ll

2 ↗

(On Diff #303894)

I'd prefer adding one more RUN line instead of duplicating the file.

[ab]

Rebased, split tests by intrinsic rather than by GISel vs SDAG (since GISel is now always built and we don't need the separate test directory)

[apazos]

I wonder if we could have these tests be generic for aarch64 target.
These intrinsics implementation don't have anything dependent on Apple ABI.

[ab]

In D91087#3097889, @apazos wrote:

I wonder if we could have these tests be generic for aarch64 target.
These intrinsics implementation don't have anything dependent on Apple ABI.

That ship has sailed I think ;) A large chunk of tests use different targets depending on who wrote them, and I guess that's okay precisely because the target differences aren't relevant to the tests.
That's a lot less true for the logic around lowering global references and constants and whatnot, I'm sure that looks quite different for non-darwin (and maybe that'll be enough to justify splitting the test file altogether, the ones I have for those features cover a lot of darwin-specific subtleties that aren't relevant elsewhere)

[danielkiss]

LGTM, any triplet could work here, where it matters we can add a new RUN line with an other triplet.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
   let Inst{31} = 0;
 }
 
 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
     : BaseOneOperandData<opc, GPR64, asm, node> {
   let Inst{31} = 1;
 }
 
-class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm>
-  : I<(outs GPR64:$Rd), (ins GPR64:$src, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
-      "$Rd = $src",
-      []>,
+class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm,
+                      SDPatternOperator op>
+  : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
+      "$dst = $Rd", [(set GPR64:$dst, (op GPR64:$Rd, opcode, GPR64sp:$Rn))]>,
     Sched<[WriteI, ReadI]> {
   bits<5> Rd;
   bits<5> Rn;
   let Inst{31-15} = 0b11011010110000010;
   let Inst{14-12} = opcode_prefix;
   let Inst{11-10} = opcode;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rd;
 }
 
-class SignAuthZero<bits<3> opcode_prefix, bits<2> opcode, string asm>
-  : I<(outs GPR64:$Rd), (ins GPR64:$src), asm, "\t$Rd", "$Rd = $src",
-      []>, Sched<[]> {
+class SignAuthZero<bits<3> opcode_prefix, bits<2> opcode, string asm,
+                   SDPatternOperator op>
+  : I<(outs GPR64:$dst), (ins GPR64:$Rd), asm, "\t$Rd", "$dst = $Rd",
+      [(set GPR64:$dst, (op GPR64:$Rd, opcode, (i64 0)))]>,
+    Sched<[]> {
   bits<5> Rd;
   let Inst{31-15} = 0b11011010110000010;
   let Inst{14-12} = opcode_prefix;
   let Inst{11-10} = opcode;
   let Inst{9-5} = 0b11111;
   let Inst{4-0} = Rd;
 }
 

llvm/lib/Target/AArch64/AArch64InstrInfo.td

let Predicates = [HasPAuth] in {
   def : InstAlias<"autiasp", (AUTIASP), 1>;
   def : InstAlias<"autibsp", (AUTIBSP), 1>;
   def : InstAlias<"pacia1716", (PACIA1716), 1>;
   def : InstAlias<"pacib1716", (PACIB1716), 1>;
   def : InstAlias<"autia1716", (AUTIA1716), 1>;
   def : InstAlias<"autib1716", (AUTIB1716), 1>;
   def : InstAlias<"xpaclri", (XPACLRI), 1>;
 
-  multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {
-    def IA   : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
-    def IB   : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
-    def DA   : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>;
-    def DB   : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>;
-    def IZA  : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>;
-    def DZA  : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>;
-    def IZB  : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>;
-    def DZB  : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb")>;
+  multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm,
+                      SDPatternOperator op> {
+    def IA   : SignAuthOneData<prefix, 0b00, !strconcat(asm,  "ia"), op>;
+    def IB   : SignAuthOneData<prefix, 0b01, !strconcat(asm,  "ib"), op>;
+    def DA   : SignAuthOneData<prefix, 0b10, !strconcat(asm,  "da"), op>;
+    def DB   : SignAuthOneData<prefix, 0b11, !strconcat(asm,  "db"), op>;
+    def IZA  : SignAuthZero<prefix_z,  0b00, !strconcat(asm, "iza"), op>;
+    def DZA  : SignAuthZero<prefix_z,  0b10, !strconcat(asm, "dza"), op>;
+    def IZB  : SignAuthZero<prefix_z,  0b01, !strconcat(asm, "izb"), op>;
+    def DZB  : SignAuthZero<prefix_z,  0b11, !strconcat(asm, "dzb"), op>;
   }
 
-  defm PAC : SignAuth<0b000, 0b010, "pac">;
-  defm AUT : SignAuth<0b001, 0b011, "aut">;
+  defm PAC : SignAuth<0b000, 0b010, "pac", int_ptrauth_sign>;
+  defm AUT : SignAuth<0b001, 0b011, "aut", null_frag>;
 
   def XPACI : ClearAuth<0, "xpaci">;
   def XPACD : ClearAuth<1, "xpacd">;
-  def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>;
+
+  def PACGA : SignAuthTwoOperand<0b1100, "pacga", int_ptrauth_sign_generic>;
 
   // Combined Instructions
   let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1  in {
     def BRAA    : AuthBranchTwoOperands<0, 0, "braa">;
     def BRAB    : AuthBranchTwoOperands<0, 1, "brab">;
   }
   let isCall = 1, Defs = [LR], Uses = [SP] in {
     def BLRAA   : AuthBranchTwoOperands<1, 0, "blraa">;

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

if (DstReg != I.getOperand(0).getReg()) {
       MIB.buildCopy({I.getOperand(0)}, {DstReg});
       RBI.constrainGenericRegister(I.getOperand(0).getReg(),
                                    AArch64::GPR32RegClass, MRI);
     }
 
     I.eraseFromParent();
     return true;
   }
+  case Intrinsic::ptrauth_sign: {
+    Register DstReg = I.getOperand(0).getReg();
+    Register ValReg = I.getOperand(2).getReg();
+    uint64_t Key = I.getOperand(3).getImm();
+    Register DiscReg = I.getOperand(4).getReg();
+    auto DiscVal = getIConstantVRegVal(DiscReg, MRI);
+    bool IsDiscZero = DiscVal.hasValue() && DiscVal->isNullValue();
+
+    if (Key > 3)
+      return false;
+
+    unsigned Opcodes[][4] = {
+        {AArch64::PACIA, AArch64::PACIB, AArch64::PACDA, AArch64::PACDB},
+        {AArch64::PACIZA, AArch64::PACIZB, AArch64::PACDZA, AArch64::PACDZB}};
+    unsigned Opcode = Opcodes[IsDiscZero][Key];
+
+    auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg});
+
+    if (!IsDiscZero) {
+      PAC.addUse(DiscReg);
+      RBI.constrainGenericRegister(DiscReg, AArch64::GPR64spRegClass, MRI);
+    }
+
+    RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
+    I.eraseFromParent();
+    return true;
+  }
   case Intrinsic::frameaddress:
   case Intrinsic::returnaddress: {
     MachineFunction &MF = *I.getParent()->getParent();
     MachineFrameInfo &MFI = MF.getFrameInfo();
 
     unsigned Depth = I.getOperand(2).getImm();
     Register DstReg = I.getOperand(0).getReg();
     RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);

llvm/test/CodeGen/AArch64/ptrauth-intrinsic-sign-generic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=0 | FileCheck %s
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s
+
+define i64 @test_sign_generic(i64 %arg, i64 %arg1) {
+; CHECK-LABEL: test_sign_generic:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacga x0, x0, x1
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign.generic(i64 %arg, i64 %arg1)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.ptrauth.sign.generic(i64, i64)

llvm/test/CodeGen/AArch64/ptrauth-intrinsic-sign.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=0 | FileCheck %s
+; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s
+
+define i64 @test_sign_ia(i64 %arg, i64 %arg1) {
+; CHECK-LABEL: test_sign_ia:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacia x0, x1
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 0, i64 %arg1)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_ia_zero(i64 %arg) {
+; CHECK-LABEL: test_sign_ia_zero:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    paciza x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 0, i64 0)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_ib(i64 %arg, i64 %arg1) {
+; CHECK-LABEL: test_sign_ib:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacib x0, x1
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 1, i64 %arg1)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_ib_zero(i64 %arg) {
+; CHECK-LABEL: test_sign_ib_zero:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacizb x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 1, i64 0)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_da(i64 %arg, i64 %arg1) {
+; CHECK-LABEL: test_sign_da:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacda x0, x1
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 2, i64 %arg1)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_da_zero(i64 %arg) {
+; CHECK-LABEL: test_sign_da_zero:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacdza x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 2, i64 0)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_db(i64 %arg, i64 %arg1) {
+; CHECK-LABEL: test_sign_db:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacdb x0, x1
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 3, i64 %arg1)
+  ret i64 %tmp
+}
+
+define i64 @test_sign_db_zero(i64 %arg) {
+; CHECK-LABEL: test_sign_db_zero:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    pacdzb x0
+; CHECK-NEXT:    ret
+  %tmp = call i64 @llvm.ptrauth.sign(i64 %arg, i32 3, i64 0)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.ptrauth.sign(i64, i32, i64)