[X86] Add missing code in D89102 [X86] Add HRESET instruction.

[craig.topper]

llvm/lib/Target/X86/X86.td

770

Section 1.3 INSTRUCTION SET EXTENSIONS AND FEATURE INTRODUCTION IN INTEL®
64 AND IA-32 PROCESSORS in Intel® Architecture Instruction Set Extensions Programming Reference does not show this instruction being supported on Sapphire Rapids. Is the documentation incorrect or is this change incorrect?

[pengfei]

HRESET is not supported on Sapphire Rapids. Thanks for pointing it out.

clang/docs/ReleaseNotes.rst

 - Support for ``-march=x86-64-v[234]`` has been added.
   See :doc:`UsersManual` for details about these micro-architecture levels.
 
 - The -mtune command line option is no longer ignored for X86. This can be used
   to request microarchitectural optimizations independent on -march. -march=<cpu>
   implies -mtune=<cpu>. -mtune=generic is the default with no -march or -mtune
   specified.
 
+- Support for ISA HRESET has been added.
+
 Internal API Changes
 --------------------
 
 These are major API changes that have happened since the 11.0.0 release of
 Clang. If upgrading an external codebase that uses Clang as a library,
 this section should help get you past the largest hurdles of upgrading.
 
 - ...

clang/test/Preprocessor/predefined-arch-macros.c

 // CHECK_SPR_M32: #define __BMI__ 1
 // CHECK_SPR_M32: #define __CLDEMOTE__ 1
 // CHECK_SPR_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SPR_M32: #define __CLWB__ 1
 // CHECK_SPR_M32: #define __ENQCMD__ 1
 // CHECK_SPR_M32: #define __F16C__ 1
 // CHECK_SPR_M32: #define __FMA__ 1
 // CHECK_SPR_M32: #define __GFNI__ 1
+// CHECK_SPR_M32: #define __HRESET__ 1
 // CHECK_SPR_M32: #define __INVPCID__ 1
 // CHECK_SPR_M32: #define __LZCNT__ 1
 // CHECK_SPR_M32: #define __MMX__ 1
 // CHECK_SPR_M32: #define __MOVBE__ 1
 // CHECK_SPR_M32: #define __PCLMUL__ 1
 // CHECK_SPR_M32: #define __PCONFIG__ 1
 // CHECK_SPR_M32: #define __PKU__ 1
 // CHECK_SPR_M32: #define __POPCNT__ 1

 // CHECK_SPR_M64: #define __BMI__ 1
 // CHECK_SPR_M64: #define __CLDEMOTE__ 1
 // CHECK_SPR_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SPR_M64: #define __CLWB__ 1
 // CHECK_SPR_M64: #define __ENQCMD__ 1
 // CHECK_SPR_M64: #define __F16C__ 1
 // CHECK_SPR_M64: #define __FMA__ 1
 // CHECK_SPR_M64: #define __GFNI__ 1
+// CHECK_SPR_M64: #define __HRESET__ 1
 // CHECK_SPR_M64: #define __INVPCID__ 1
 // CHECK_SPR_M64: #define __LZCNT__ 1
 // CHECK_SPR_M64: #define __MMX__ 1
 // CHECK_SPR_M64: #define __MOVBE__ 1
 // CHECK_SPR_M64: #define __PCLMUL__ 1
 // CHECK_SPR_M64: #define __PCONFIG__ 1
 // CHECK_SPR_M64: #define __PKU__ 1
 // CHECK_SPR_M64: #define __POPCNT__ 1

llvm/lib/Support/X86TargetParser.cpp

 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
constexpr FeatureBitset FeaturesICLServer =
     FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
 constexpr FeatureBitset FeaturesTigerlake =
     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
     FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
 constexpr FeatureBitset FeaturesSapphireRapids =
     FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
     FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
-    FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
+    FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG |
+    FeatureHRESET;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
 constexpr FeatureBitset FeaturesSilvermont =
     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
 constexpr FeatureBitset FeaturesGoldmont =

llvm/lib/Target/X86/X86.td

def ProcessorFeatures {
   list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
                                                   FeatureAMXINT8,
                                                   FeatureAMXBF16,
                                                   FeatureBF16,
                                                   FeatureSERIALIZE,
                                                   FeatureCLDEMOTE,
                                                   FeatureWAITPKG,
                                                   FeaturePTWRITE,
+                                                  FeatureHRESET,
                                                   FeatureTSXLDTRK,
                                                   FeatureENQCMD,
                                                   FeatureSHSTK,
                                                   FeatureVP2INTERSECT,
                                                   FeatureMOVDIRI,
                                                   FeatureMOVDIR64B];
   list<SubtargetFeature> SPRTuning = ICXTuning;
   list<SubtargetFeature> SPRFeatures =