[SDag] SimplifyDemandedBits: simplify to FP constant if all bits known

[foad]

Summary

We were already doing this for integer constants. This patch implements
the same thing for floating point constants.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2263–2264

Would fixing this FIXME do the same thing?

[foad]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2263–2264

Aha! I thought this should be done centrally somewhere. I'll give this a try, thanks.

[foad]

Reimplement as suggested.

[foad]

This looks like a clear win to me on all the affected test cases except for one slight regression noted inline.

llvm/test/CodeGen/ARM/fcopysign.ll

98–101

I'm not an ARM expert but this slight regression looks like it's just bad luck in the register allocator. If the vmov went into d1 then we could use vbit instead of vorr+vbsl.

[spatel]

(adding more potential ARM reviewers)

[RKSimon]

llvm/test/CodeGen/X86/uint_to_fp-2.ll

11

@craig.topper @spatel This looks like we're loading the same constant as (double x) and <double x, double ???> - do you know if we already have examples of this or is this a new type of regression?

[dmgreen]

llvm/test/CodeGen/ARM/fcopysign.ll

98–101

Yeah this can happen... It's a bit of a shame but doesn't look like the fault of this patch, exactly. BSL/BIT/BIF are selected best-effort using a pseudo.

[spatel]

llvm/test/CodeGen/X86/uint_to_fp-2.ll

11

We might avoid that by checking number of uses of the constant?

Looks like a general shortcoming of combining/hoisting constants:

$ cat vec_const.ll 
define <4 x i32> @f(<4 x i32> %x) {
  %a1 = add <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
  %a2 = xor <4 x i32> %a1, <i32 1, i32 2, i32 3, i32 undef>
  ret <4 x i32> %a2
}
$ llc -o - vec_const.ll 
	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 10, 15
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function f
LCPI0_0:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	3                               ## 0x3
	.long	4                               ## 0x4
LCPI0_1:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	3                               ## 0x3
	.space	4
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_f
	.p2align	4, 0x90
_f:                                     ## @f
	.cfi_startproc
## %bb.0:
	paddd	LCPI0_0(%rip), %xmm0
	pxor	LCPI0_1(%rip), %xmm0
	retq

[RKSimon]

llvm/test/CodeGen/X86/uint_to_fp-2.ll

11

Thanks, I've raised a bug at https://bugs.llvm.org/show_bug.cgi?id=47744

[RKSimon]

LGTM, cheers - looks like the minor arm/x86 issues are already common and nothing really attributable to this patch.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

bool TargetLowering::SimplifyDemandedBits(
 
   if (Op.getOpcode() == ISD::Constant) {
     // We know all of the bits for a constant!
     Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
     Known.Zero = ~Known.One;
     return false;
   }
 
+  if (Op.getOpcode() == ISD::ConstantFP) {
+    // We know all of the bits for a floating point constant!
+    Known.One = cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt();
+    Known.Zero = ~Known.One;
+    return false;
+  }
+
   // Other users may use these bits.
   EVT VT = Op.getValueType();
   if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
     if (Depth != 0) {
       // If not at the root, Just compute the Known bits to
       // simplify things downstream.
       Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
       return false;
if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) {
     const SDNode *N = Op.getNode();
     for (SDNodeIterator I = SDNodeIterator::begin(N),
                         E = SDNodeIterator::end(N);
          I != E; ++I) {
       SDNode *Op = *I;
       if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
         if (C->isOpaque())
           return false;
     }
-    // TODO: Handle float bits as well.
     if (VT.isInteger())
       return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
+    if (VT.isFloatingPoint())
+      return TLO.CombineTo(
+          Op,
+          TLO.DAG.getConstantFP(
+              APFloat(TLO.DAG.EVTToAPFloatSemantics(VT), Known.One), dl, VT));
   }
 
   return false;
 }
 
 bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
                                                 const APInt &DemandedElts,
                                                 APInt &KnownUndef,

llvm/test/CodeGen/ARM/fcopysign.ll

 ; HARD:       @ %bb.0: @ %entry
 ; HARD-NEXT:    .save {r11, lr}
 ; HARD-NEXT:    push {r11, lr}
 ; HARD-NEXT:    bl bar
 ; HARD-NEXT:    vmov d16, r0, r1
 ; HARD-NEXT:    vcvt.f32.f64 s0, d16
 ; HARD-NEXT:    vmov.i32 d17, #0x80000000
 ; HARD-NEXT:    vshr.u64 d16, d16, #32
-; HARD-NEXT:    vmov.f32 s2, #5.000000e-01
-; HARD-NEXT:    vbit d1, d16, d17
+; HARD-NEXT:    vmov.i32 d18, #0x3f000000
+; HARD-NEXT:    vorr d1, d17, d17
+; HARD-NEXT:    vbsl d1, d16, d18
 ; HARD-NEXT:    vadd.f32 s0, s0, s2
 ; HARD-NEXT:    pop {r11, pc}
 entry:
   %0 = tail call double (...) @bar() nounwind
   %1 = fptrunc double %0 to float
   %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
   %3 = fadd float %1, %2
   ret float %3
 }
 
 declare double @bar(...)
 declare double @copysign(double, double) nounwind
 declare float @copysignf(float, float) nounwind

llvm/test/CodeGen/X86/combine-bextr.ll

 
 define float @bextr_uitofp(i32 %x, i32 %y) {
 ; X32-LABEL: bextr_uitofp:
 ; X32:       # %bb.0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movl $3855, %eax # imm = 0xF0F
 ; X32-NEXT:    bextrl %eax, {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
-; X32-NEXT:    movd %eax, %xmm1
-; X32-NEXT:    por %xmm0, %xmm1
-; X32-NEXT:    subsd %xmm0, %xmm1
-; X32-NEXT:    xorps %xmm0, %xmm0
-; X32-NEXT:    cvtsd2ss %xmm1, %xmm0
+; X32-NEXT:    movd %eax, %xmm0
+; X32-NEXT:    por {{\.LCPI.*}}, %xmm0
+; X32-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; X32-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; X32-NEXT:    movss %xmm0, (%esp)
 ; X32-NEXT:    flds (%esp)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: bextr_uitofp:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl $3855, %eax # imm = 0xF0F
 ; X64-NEXT:    bextrl %eax, %edi, %eax
 ; X64-NEXT:    cvtsi2ss %eax, %xmm0
 ; X64-NEXT:    retq
   %1 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 3855)
   %2 = uitofp i32 %1 to float
   ret float %2
 }

llvm/test/CodeGen/X86/copysign-constant-magnitude.ll

 }
 
 ; CHECK:        [[SIGNMASK2:L.+]]:
 ; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 
 define double @mag_neg0_double(double %x) nounwind {
 ; CHECK-LABEL: mag_neg0_double:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT:    andps %xmm1, %xmm0
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double -0.0, double %x)
   ret double %y
 }
 
 ; CHECK:        [[SIGNMASK3:L.+]]:
 ; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 ; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 ; CHECK:        [[ONE3:L.+]]:
 ; CHECK-NEXT:   .quad 0x3ff0000000000000     ## double 1
 
 define double @mag_pos1_double(double %x) nounwind {
 ; CHECK-LABEL: mag_pos1_double:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double 1.0, double %x)
   ret double %y
 }
 
 ; CHECK:        [[SIGNMASK4:L.+]]:
 ; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 ; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0

 }
 
 ; CHECK:       [[SIGNMASK6:L.+]]:
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 
 define float @mag_neg0_float(float %x) nounwind {
 ; CHECK-LABEL: mag_neg0_float:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    andps %xmm1, %xmm0
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float -0.0, float %x)
   ret float %y
 }
 
 ; CHECK:       [[SIGNMASK7:L.+]]:
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK:        [[ONE7:L.+]]:
 ; CHECK-NEXT:  .long 0x3f800000              ## float 1
 
 define float @mag_pos1_float(float %x) nounwind {
 ; CHECK-LABEL: mag_pos1_float:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    orps %xmm1, %xmm0
+; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float 1.0, float %x)
   ret float %y
 }
 
 ; CHECK:       [[SIGNMASK8:L.+]]:
 ; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK-NEXT:  .long 0x80000000              ## float -0

llvm/test/CodeGen/X86/fp-intrinsics.ll

 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uifdi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    subl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 16
-; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X86-SSE-NEXT:    orpd %xmm0, %xmm1
-; X86-SSE-NEXT:    subsd %xmm0, %xmm1
-; X86-SSE-NEXT:    movsd %xmm1, (%esp)
+; X86-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-SSE-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
 ; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uifdi:
 ; SSE:       # %bb.0: # %entry

 ; X87-NEXT:    addl $12, %esp
 ; X87-NEXT:    .cfi_def_cfa_offset 4
 ; X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: uiffi:
 ; X86-SSE:       # %bb.0: # %entry
 ; X86-SSE-NEXT:    pushl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 8
-; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X86-SSE-NEXT:    orpd %xmm0, %xmm1
-; X86-SSE-NEXT:    subsd %xmm0, %xmm1
-; X86-SSE-NEXT:    xorps %xmm0, %xmm0
-; X86-SSE-NEXT:    cvtsd2ss %xmm1, %xmm0
+; X86-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-SSE-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; X86-SSE-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; X86-SSE-NEXT:    movss %xmm0, (%esp)
 ; X86-SSE-NEXT:    flds (%esp)
 ; X86-SSE-NEXT:    wait
 ; X86-SSE-NEXT:    popl %eax
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; SSE-LABEL: uiffi:

llvm/test/CodeGen/X86/fp-round.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512
 
 define float @round_f32(float %x) {
 ; SSE2-LABEL: round_f32:
 ; SSE2:       ## %bb.0:
 ; SSE2-NEXT:    jmp _roundf ## TAILCALL
 ;
 ; SSE41-LABEL: round_f32:
 ; SSE41:       ## %bb.0:
 ; SSE41-NEXT:    movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
 ; SSE41-NEXT:    andps %xmm0, %xmm1
-; SSE41-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSE41-NEXT:    orps %xmm1, %xmm2
-; SSE41-NEXT:    addss %xmm0, %xmm2
+; SSE41-NEXT:    orps {{.*}}(%rip), %xmm1
+; SSE41-NEXT:    addss %xmm0, %xmm1
 ; SSE41-NEXT:    xorps %xmm0, %xmm0
-; SSE41-NEXT:    roundss $11, %xmm2, %xmm0
+; SSE41-NEXT:    roundss $11, %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: round_f32:
 ; AVX1:       ## %bb.0:
 ; AVX1-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm1
 ; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm2 = [4.9999997E-1,4.9999997E-1,4.9999997E-1,4.9999997E-1]
 ; AVX1-NEXT:    vorps %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vaddss %xmm1, %xmm0, %xmm0

 ; SSE2-LABEL: round_f64:
 ; SSE2:       ## %bb.0:
 ; SSE2-NEXT:    jmp _round ## TAILCALL
 ;
 ; SSE41-LABEL: round_f64:
 ; SSE41:       ## %bb.0:
 ; SSE41-NEXT:    movapd {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
 ; SSE41-NEXT:    andpd %xmm0, %xmm1
-; SSE41-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
-; SSE41-NEXT:    orpd %xmm1, %xmm2
-; SSE41-NEXT:    addsd %xmm0, %xmm2
+; SSE41-NEXT:    orpd {{.*}}(%rip), %xmm1
+; SSE41-NEXT:    addsd %xmm0, %xmm1
 ; SSE41-NEXT:    xorps %xmm0, %xmm0
-; SSE41-NEXT:    roundsd $11, %xmm2, %xmm0
+; SSE41-NEXT:    roundsd $11, %xmm1, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: round_f64:
 ; AVX:       ## %bb.0:
 ; AVX-NEXT:    vandpd {{.*}}(%rip), %xmm0, %xmm1
 ; AVX-NEXT:    vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
 ; AVX-NEXT:    ## xmm2 = mem[0,0]
 ; AVX-NEXT:    vorpd %xmm1, %xmm2, %xmm1

llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll

; X87-NEXT:    retl
   ret float %result
 }
 
 define float @uitofp_i32tof32(i32 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i32tof32:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE-X86-NEXT:    orpd %xmm0, %xmm1
-; SSE-X86-NEXT:    subsd %xmm0, %xmm1
-; SSE-X86-NEXT:    xorps %xmm0, %xmm0
-; SSE-X86-NEXT:    cvtsd2ss %xmm1, %xmm0
+; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-X86-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; SSE-X86-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; SSE-X86-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; SSE-X86-NEXT:    movss %xmm0, (%esp)
 ; SSE-X86-NEXT:    flds (%esp)
 ; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    popl %eax
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i32tof32:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movl %edi, %eax
 ; SSE-X64-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX1-X86-LABEL: uitofp_i32tof32:
 ; AVX1-X86:       # %bb.0:
 ; AVX1-X86-NEXT:    pushl %eax
 ; AVX1-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-X86-NEXT:    vorpd %xmm0, %xmm1, %xmm1
-; AVX1-X86-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
+; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX1-X86-NEXT:    vorpd {{\.LCPI.*}}, %xmm0, %xmm0
+; AVX1-X86-NEXT:    vsubsd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vcvtsd2ss %xmm0, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vmovss %xmm0, (%esp)
 ; AVX1-X86-NEXT:    flds (%esp)
 ; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    popl %eax
 ; AVX1-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX1-X86-NEXT:    retl
 ;

 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-X86-NEXT:    .cfi_offset %ebp, -8
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE-X86-NEXT:    orpd %xmm0, %xmm1
-; SSE-X86-NEXT:    subsd %xmm0, %xmm1
-; SSE-X86-NEXT:    movsd %xmm1, (%esp)
+; SSE-X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-X86-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; SSE-X86-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movl %ebp, %esp
 ; SSE-X86-NEXT:    popl %ebp
 ; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i32tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movl %edi, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %rax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX1-X86-LABEL: uitofp_i32tof64:
 ; AVX1-X86:       # %bb.0:
 ; AVX1-X86-NEXT:    pushl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa_offset 8
 ; AVX1-X86-NEXT:    .cfi_offset %ebp, -8
 ; AVX1-X86-NEXT:    movl %esp, %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa_register %ebp
 ; AVX1-X86-NEXT:    andl $-8, %esp
 ; AVX1-X86-NEXT:    subl $8, %esp
-; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-X86-NEXT:    vorpd %xmm0, %xmm1, %xmm1
-; AVX1-X86-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
+; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX1-X86-NEXT:    vorpd {{\.LCPI.*}}, %xmm0, %xmm0
+; AVX1-X86-NEXT:    vsubsd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX1-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX1-X86-NEXT:    fldl (%esp)
 ; AVX1-X86-NEXT:    wait
 ; AVX1-X86-NEXT:    movl %ebp, %esp
 ; AVX1-X86-NEXT:    popl %ebp
 ; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4
 ; AVX1-X86-NEXT:    retl
 ;

llvm/test/CodeGen/X86/fp128-cast.ll

 ; X64-SSE-LABEL: TestTruncCopysign:
 ; X64-SSE:       # %bb.0: # %entry
 ; X64-SSE-NEXT:    cmpl $50001, %edi # imm = 0xC351
 ; X64-SSE-NEXT:    jl .LBB26_2
 ; X64-SSE-NEXT:  # %bb.1: # %if.then
 ; X64-SSE-NEXT:    pushq %rax
 ; X64-SSE-NEXT:    callq __trunctfdf2
 ; X64-SSE-NEXT:    andps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
-; X64-SSE-NEXT:    orps %xmm1, %xmm0
+; X64-SSE-NEXT:    orps {{.*}}(%rip), %xmm0
 ; X64-SSE-NEXT:    callq __extenddftf2
 ; X64-SSE-NEXT:    addq $8, %rsp
 ; X64-SSE-NEXT:  .LBB26_2: # %cleanup
 ; X64-SSE-NEXT:    retq
 ;
 ; X32-LABEL: TestTruncCopysign:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    pushl %edi

llvm/test/CodeGen/X86/scalar-int-to-fp.ll

 ; AVX512_64-LABEL: u32_to_f:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtusi2ss %edi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; SSE2_32-LABEL: u32_to_f:
 ; SSE2_32:       # %bb.0:
 ; SSE2_32-NEXT:    pushl %eax
-; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2_32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE2_32-NEXT:    orpd %xmm0, %xmm1
-; SSE2_32-NEXT:    subsd %xmm0, %xmm1
-; SSE2_32-NEXT:    xorps %xmm0, %xmm0
-; SSE2_32-NEXT:    cvtsd2ss %xmm1, %xmm0
+; SSE2_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2_32-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; SSE2_32-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; SSE2_32-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; SSE2_32-NEXT:    movss %xmm0, (%esp)
 ; SSE2_32-NEXT:    flds (%esp)
 ; SSE2_32-NEXT:    popl %eax
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: u32_to_f:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    movl %edi, %eax

 ; AVX512_64-NEXT:    retq
 ;
 ; SSE2_32-LABEL: u32_to_d:
 ; SSE2_32:       # %bb.0:
 ; SSE2_32-NEXT:    pushl %ebp
 ; SSE2_32-NEXT:    movl %esp, %ebp
 ; SSE2_32-NEXT:    andl $-8, %esp
 ; SSE2_32-NEXT:    subl $8, %esp
-; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2_32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE2_32-NEXT:    orpd %xmm0, %xmm1
-; SSE2_32-NEXT:    subsd %xmm0, %xmm1
-; SSE2_32-NEXT:    movsd %xmm1, (%esp)
+; SSE2_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2_32-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; SSE2_32-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; SSE2_32-NEXT:    movsd %xmm0, (%esp)
 ; SSE2_32-NEXT:    fldl (%esp)
 ; SSE2_32-NEXT:    movl %ebp, %esp
 ; SSE2_32-NEXT:    popl %ebp
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: u32_to_d:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    movl %edi, %eax

llvm/test/CodeGen/X86/uint_to_fp-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s
 
 ; rdar://6504833
 define float @test1(i32 %x) nounwind readnone {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %eax
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    orpd %xmm0, %xmm1
-; CHECK-NEXT:    subsd %xmm0, %xmm1
-; CHECK-NEXT:    xorps %xmm0, %xmm0
-; CHECK-NEXT:    cvtsd2ss %xmm1, %xmm0
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    orpd {{\.LCPI.*}}, %xmm0
+; CHECK-NEXT:    subsd {{\.LCPI.*}}, %xmm0
+; CHECK-NEXT:    cvtsd2ss %xmm0, %xmm0
 ; CHECK-NEXT:    movss %xmm0, (%esp)
 ; CHECK-NEXT:    flds (%esp)
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 entry:
   %0 = uitofp i32 %x to float
   ret float %0
 }
 
 ; PR10802
 define float @test2(<4 x i32> %x) nounwind readnone ssp {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    orps %xmm0, %xmm1
-; CHECK-NEXT:    subsd %xmm0, %xmm1
+; CHECK-NEXT:    orps {{\.LCPI.*}}, %xmm1
+; CHECK-NEXT:    subsd {{\.LCPI.*}}, %xmm1
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    cvtsd2ss %xmm1, %xmm0
 ; CHECK-NEXT:    movss %xmm0, (%esp)
 ; CHECK-NEXT:    flds (%esp)
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 entry:
   %vecext = extractelement <4 x i32> %x, i32 0
   %conv = uitofp i32 %vecext to float
   ret float %conv
 }

llvm/test/CodeGen/X86/vector-shuffle-combining.ll

; AVX-NEXT:    retq
   %tmp10 = insertelement <8 x i16> %tmp9, i16 %cvt1, i32 5
   %tmp11 = insertelement <8 x i16> %tmp10, i16 %cvt2, i32 6
   %tmp12 = insertelement <8 x i16> %tmp11, i16 undef, i32 7
   %tmp13 = shufflevector <8 x i16> %tmp12, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %tmp13
 }
 
 define void @PR43024() {
-; SSE2-LABEL: PR43024:
-; SSE2:       # %bb.0:
-; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
-; SSE2-NEXT:    movaps %xmm0, (%rax)
-; SSE2-NEXT:    movaps %xmm0, %xmm1
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
-; SSE2-NEXT:    addss %xmm0, %xmm1
-; SSE2-NEXT:    xorps %xmm0, %xmm0
-; SSE2-NEXT:    addss %xmm0, %xmm1
-; SSE2-NEXT:    addss %xmm0, %xmm1
-; SSE2-NEXT:    movss %xmm1, (%rax)
-; SSE2-NEXT:    retq
-;
-; SSSE3-LABEL: PR43024:
-; SSSE3:       # %bb.0:
-; SSSE3-NEXT:    movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
-; SSSE3-NEXT:    movaps %xmm0, (%rax)
-; SSSE3-NEXT:    movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSSE3-NEXT:    addss %xmm0, %xmm1
-; SSSE3-NEXT:    xorps %xmm0, %xmm0
-; SSSE3-NEXT:    addss %xmm0, %xmm1
-; SSSE3-NEXT:    addss %xmm0, %xmm1
-; SSSE3-NEXT:    movss %xmm1, (%rax)
-; SSSE3-NEXT:    retq
-;
-; SSE41-LABEL: PR43024:
-; SSE41:       # %bb.0:
-; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
-; SSE41-NEXT:    movaps %xmm0, (%rax)
-; SSE41-NEXT:    movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE41-NEXT:    addss %xmm0, %xmm1
-; SSE41-NEXT:    xorps %xmm0, %xmm0
-; SSE41-NEXT:    addss %xmm0, %xmm1
-; SSE41-NEXT:    addss %xmm0, %xmm1
-; SSE41-NEXT:    movss %xmm1, (%rax)
-; SSE41-NEXT:    retq
+; SSE-LABEL: PR43024:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
+; SSE-NEXT:    movaps %xmm0, (%rax)
+; SSE-NEXT:    addss {{.*}}(%rip), %xmm0
+; SSE-NEXT:    xorps %xmm1, %xmm1
+; SSE-NEXT:    addss %xmm1, %xmm0
+; SSE-NEXT:    addss %xmm1, %xmm0
+; SSE-NEXT:    movss %xmm0, (%rax)
+; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR43024:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
 ; AVX-NEXT:    vmovaps %xmm0, (%rax)
 ; AVX-NEXT:    vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
 ; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0