- User Since
- Jul 24 2020, 1:28 AM (47 w, 4 h)
@fhahn I don't think that would be possible, at least not in our case, since it won't actually reach that line.
@SjoerdMeijer, in response to your questions, yes I added the check to see if a base register is used/modified on line 1698/1699 so that we still perform that legality check as we won't reach the one on 1726 if the renaming of registers is successful. Also, the modified base register test is taken from the reproducer and so it should no longer generate extra, unwanted STPs.
Fixed the style points raised in the helper function updateFlagsWithRenameReg and in the test consthoist-gep.ll
Tue, Jun 15
Added checks to ensure that STPs are only generated when the base register is not in use or has not been modified. Also added test cases when the base register has been modified and when there are no registers available for renaming.
Wed, Jun 9
@fhahn in response to your inline comment about performing the renaming registers check twice, if we don't have it we won't try to rename the registers at all, since the check on line 1764 is not reached in our case as we never enter the if statement that contains it. So we brought it earlier to make sure that it tries to rename the registers, if it can. I'll follow-up the rest of the comments in a new diff.
Tue, Jun 8
Changed patch title, moved tests to stp-opt-with-renaming.mir and corrected the function name and comment for the helper function in AArch64LoadStoreOptimizer.cpp
Mon, Jun 7
Removed llc test and also removed alignment check for values greater than 16. Updated the tests that failed because of this change with the new assembly now that the STP instruction is being generated.
Thu, Jun 3
Added the inline comment to explain the changes, also added an MIR test as well as changing the existing test to show the difference when aarch64-load-store-renaming is enabled.
Oct 2 2020
Oct 1 2020
Closed by revision https://reviews.llvm.org/rG20283ff491a4
Closed by revision https://reviews.llvm.org/rG545de56f87f5
Closed by revision https://reviews.llvm.org/rGdd519bf0b074
Sep 30 2020
Sorry, didn't realise tags and reviewers were automatically added. Thought it was a mistake. Apologies for the few extra emails notifications that would have been sent.
Sep 28 2020
Sep 24 2020
Renamed ARMssatnoshift and ARMusatnoshift to ARMssat and ARMusat
Sep 23 2020
Sep 22 2020
Sep 21 2020
Added new helper function isSSATMinMaxPattern which checks whether the instruction being passed in is a valid max instruction that is part of a min(max()) or max(min()) pattern. Simplified getIntImmCostInst down to make a call to this function.
Improved getIntImmCostInst so that the max(min()) case is properly handled by checking the instruction's operand is a min and a select instruction.
Sep 16 2020
Made the checks more specific to min(max()) and max(min()) patterns which should generate SSAT
Sep 15 2020
Sep 14 2020
Sep 10 2020
Added explanation about LLVM canonicalizing to min/max patterns to both the comment before the function and commit message. Tidied up formatting by moving a comment, reducing indention where possible and removing unused function (isUpperSaturate).
Sep 9 2020
Aug 19 2020
Aug 12 2020
Changed tests to show original IR (vmlav and add instructions) being transformed to use vmlava, run using opt -instcombine -S -mtriple=arm -o - %s instead.
Aug 4 2020
Aug 3 2020
Removed t2_asr_imm and replaced with just asr_imm. Also deleted thumb2 tests and instead included Run command in arm tests to avoid having the same tests repeated.
Jul 24 2020
Removed fast attributes and added test cases for when the floating point flag is not set.
Added second test for f16 case and made test cases much shorter. Also moved position of pattern definition so that the size is handled clearly