[LLD][PowerPC] Implement GOT to PC-Rel relaxation

[nemanjai]

Summary

This patch implements the handling for the R_PPC64_PCREL_OPT relocation as well as the GOT relocation for the associated R_PPC64_GOT_PCREL34 relocation.

On Power10 targets with PC-Relative addressing, the linker can relax GOT-relative accesses to PC-Relative under some conditions. Since the sequence consists of a prefixed load, followed by a non-prefixed access (load or store), the linker needs to replace the first instruction (as the replacement instruction will be prefixed). The compiler communicates to the linker that this optimization is safe by placing the two aforementioned relocations on the GOT load (of the address).
The linker then does two things:

1. Convert the load from the got into a PC-Relative add to compute the address relative to the PC
2. Find the instruction referred to by the second relocation (R_PPC64_PCREL_OPT) and replace the first with the PC-Relative version of it

It is important to synchronize the mapping from legacy memory instructions to their PC-Relative form. Hence, this patch adds a file to be included by both the compiler and the linker so they're always in agreement.

[nemanjai]

lld/ELF/Arch/PPC64.cpp

42

Perhaps this entire enum should just be absorbed into the new one to eliminate confusion.

[nemanjai]

Add test cases for all the different instructions - thanks for your help producing these @NeHuang.
Run clang-format on the patch since the pre-commit build flagged a bunch of issues.

[stefanp]

Overall I think this looks good. I had a handful of comments but nothing major.
I wish we had a better way of doing the conversion between the old forms and the PCRel forms but I can't think of a better way.

[stefanp]

lld/ELF/Arch/PPC64.cpp

42

My two cents:
I would agree except that the file PPCLegacyToPCRelMap.def is meant specifically for PCRel (as is in the title of the file) and the update forms have nothing to do with that really...

We should clean these up but not with the PC Rel instructions.

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

73

nit:
You should probably add

DFLOADf32 = 48,  //  lfs
DFLOADf64 = 50,  //  lfd

The names DFLOADf32 and DFLOADf64 are internal names we have that won't mean anything to anyone that is not familiar with the compiler. The lfs and lfd are in the ISA.

197

I would almost prefer to have this function in the compiler in PPCPreEmitPeephole.cpp.
The function was in the compiler in the first place and it is only used in that one file.

If we do it that way we can get rid of the macro PPC_LEGACY_TO_PREFIXED_COMPILER.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

49

nit:
I get the feeling that clang-format went a little crazy on this file and removed the indentation. :)
Should probably be a separate NFC patch.

[nemanjai]

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

73

For sure. Will do.

197

I don't think it would be a good thing to get rid of that macro. I have added the #error in this file to require that one of the two be defined so that this file cannot be included accidentally somewhere else and cause namespace pollution.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

49

Yeah, I have no idea what clang-format's problem is - why is it modifying lines that I never touched in this patch? I don't mind pre-committing an NFC patch from running clang-format on this file.

[NeHuang]

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

37

nit: // Loads.

75

nit: // Stores.

124

Do we also need to add a FIXME here for PPC::LXVP and PPC::STXVP since they are not supported yet?

[NeHuang]

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

49

+1, It makes sense to have a separate NFC patch for clang-format changes. Phabricator complains those clang-format issues in https://reviews.llvm.org/D84360?id=279937

[MaskRay]

I haven't looked into the functional part of the patch. Just made some style issues and spot a few bugs due to incorrect -1lu uses.

lld/ELF/Arch/PPC64.cpp

69

return encoding >> 26;

486

Nit: uint64_t insn = readPrefixedInstruction(loc) & ~0xff000000fc000000; and move the comment below here

490

This file is not consistent on upper/lower case hexadecimals but for newer code we use lower case to be consistent with other files. The suffix lu is redundant (in any case not proper on 32-bit systems where unsigned long is 32-bit).

509

-1lu is wrong on a 32-bit platform: 4294967295.

pcRelInsn == UINT64_C(-1)

510

Consider using more errorOrWarn which can downgrade to warnings if --noinhibit-exec is implemented. error is used by code which can't really proceed. fatal is fatal error which should call exit immediately.

519

The two variables are only used once. Just write (insn & 0x0003ffff0000ffff) | pcRelInsn

lld/ELF/InputSection.cpp

1002

This is wrong on 32-bit platforms.

lld/test/ELF/Inputs/ppc64-got-to-pcrel-relaxation-def.s

4 ↗

(On Diff #280944)

.globl a, b, c, d can declare multiple variables

31 ↗

(On Diff #280944)

Are these .size and .type directives used? Dropping them can make the file much smaller

lld/test/ELF/ppc64-got-to-pcrel-relaxation.s

19 ↗

(On Diff #280944)

Some newer lld tests make sure that instructions are indented more than their containing labels

# CHECK-S-LABEL: <check_LBZ_STB>:
# CHECK-S-NEXT:    plbz 10

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

22

The parentheses are redundant

[MaskRay]

lld/test/ELF/ppc64-got-to-pcrel-relaxation.s

4 ↗

(On Diff #280944)

If a linked shared object is used to link another file, the shared object needs to specify --soname=t2 or another fixed string. Otherwise the DT_SONAME field of the other file is dependent on the full path of %t2.so, which can vary on different test machines.

[MaskRay]

lld/ELF/InputSection.cpp

1028

This assumes that relocation types on other architectures (which are represented by LLD's R_RELAX_GOT_PC or R_RELAX_GOT_PC_NOPIC) do not use the value R_PPC64_GOT_PCREL34. This is a subtle assumption we want to avoid. I think we need a new RelExpr: R_PPC64_RELAX_GOT_PCREL34.

lld/test/ELF/ppc64-got-to-pcrel-relaxation.s

168 ↗

(On Diff #280944)

Can these unrelated instructions be removed? We just need prefixed instructions and for the .reloc case, one instruction before .reloc

[nemanjai]

lld/ELF/Arch/PPC64.cpp

490

I can correct all the inconsistencies in an NFC patch after this lands. I will make sure I don't add any upper case ones.

lld/test/ELF/ppc64-got-to-pcrel-relaxation.s

168 ↗

(On Diff #280944)

I could remove them. I am reluctant to do that because the asm doesn't really make sense if we remove them. Although I realize this doesn't make a difference when linking, I just find it less visually jarring to have asm that is clearly incorrect (i.e. storing an undefined register in this case). And removing them doesn't save that many lines.

Of course, if you insist, I will remove them.

[nemanjai]

Fix up usage of unsigned long literal suffixes.
Add new rel-expr.
Fix up minor nits.
Shorten the test cases.

[nemanjai]

Remove erroneous unrelated update.

[sfertile]

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

2

This file does way more then I expect from a .def file. Are there other examples of a .def file defining so much data and code? If there isn't this needs to be moved to a header and potentially a source file since we don't want to change what a .def file represents in LLVM. If there is I still think we are better moving this to a header + source if it stay close to its current implementation using maps.

Alternatively if we split this up back to LLVM and LLD implementations it will make a clean .def fiie in lld.

My suggestion is to keep the switch in PPCPreEmitPeephole.cpp the way it is. I understand wanting to not have more then 1 place to modify when adding a new relaxable instruction is really desirable, but you have an error in LLD if we find the relocation on an unrecognized instruction to catch the mismatches. Combining both llc and lld implementations makes this much more complicated then it needs to be (and like I mentioned previously, inappropriate foe a .def file).

The LLD implementation I think we could turn into a proper .def file by working with the full encodings instead of primary opcodes and using a macro along the lines of:

MACRO(NONPCREL_ENCODING, PCREL_EQUIVALENT, OPCODE_MASK)

Then we define the enums in Arch/PPC64.cpp, and have 2 functions with switches over the NONPCREL_ENCODINGS: 1 that maps an encoding to its pc-relative equivalent encoding and one to map it to the operand mask. Instead of mixing in the bits for the non-primary opcode we just zero out the non-opcode bits, then use the 2 helper functions to implement getPCRelativeForm almost exactly the same as it is now.

As a bonus we can re-implement isInstructionUpdateForm as a macro in the .def file as well for consistency.

[nemanjai]

Need to account for a displacement on the access instruction and add some tests along the lines of

extern int Ext[40];
int test(int a) {
  return a + Ext[10];
}

lld/ELF/Arch/PPC64.cpp

515

As it turns out, the access instruction may actually have a displacement which needs to be added to the computed offset.
I will update this to account for that.

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

2

I agree with this and will rewrite this portion. This tight coupling between the compiler and the linker is quite unnecessary since there are at least two compilers on the platform and at least 3 linkers.

[nemanjai]

• Move implementation completely into LLD
• Add option to disable the optimization
• Handle computation of the total offset when the access instruction has a non-zero displacement
• Add tests with the new option as well as a test with non-zero displacement on the access instructions

[MaskRay]

lld/ELF/Options.td

407 ↗

(On Diff #283464)

Is this an option binutils will support as well?

Note that on x86, --no-relax can control whether R_X86_64_GOTPCRELX is optimized.
I hope PowerPC can adopt the same option.

There is a related thread https://sourceware.org/pipermail/binutils/2020-June/111571.html before I knew the PCREL GOT optimization activities on PowerPC.

[nemanjai]

lld/ELF/Options.td

407 ↗

(On Diff #283464)

I have asked Alan about support for this option in the GNU linkers. I'll get back to you when he responds.

I personally am not in favour of reducing the granularity by having all of this controlled by --no-relax because if we encounter bugs (or mismatches between compiler version and linker version) it is good to be able to turn off only the minimum set of optimizations.
A real example:
In Power9, we got new D-Form instructions which then ended up with relocations on them. The version of the linker in binutils on the various distros did not have support for those. Upgrading binutils was not an option for many customers, so they had to add --no-toc-optimize to their builds. If there was only --no-relax and that implied a bunch of other optimizations are turned off, such customers would be unnecessarily penalized in terms of performance.

Of course, the integration between LLD and Clang/LLVM is much more close so this particular issue is less likely to occur, but I think the argument for having finer granularity is still valid.

[sfertile]

lld/ELF/Arch/PPC64.cpp

347

Instead of shifting the primary opcode down to the least significant bits, and then shifting the secondary opcodes into the more significant bits, why don't we just use the significant opcode bits as the enum value.

For example: LDU 0xE8000001, LD = E8000000, LDU = 7C000000. It won't simplify this function since you still need the primary opcode to know how to mask out the encoding bits, but we could follow this patch with an NFC patch where we convert all the other uses of
DFormOpcd and XFormOpcode enums to use PPCInsn and get rid of the other 2 enums. If we do take this root I would suggest having separate enums for the 32-bit instructions and the prefixed instructions.

lld/ELF/Relocations.h

99 ↗

(On Diff #283464)

Should we drop the 'REL34' in the Expr? Its not really important how many bits it represents, and I think the REL is implied by 'PC' in R_RELAX_GOT_PC.

Also, should it be added to isRelExpr in Relocations.cpp?

[sfertile]

lld/ELF/Arch/PPC64.cpp

382

minor nit: The prefixed instruction in the sequence we are going to optimize should always be a paddi, since we relaxed the instruction referenced by the R_PPC64_GOT_PCREL34 from pld to paddi. My understanding could be wrong though, I expect we can only see the optimization relocation on a got-addressing sequence or a masked load/store sequence (which we don't support yet, but would also start with paddi).

[nemanjai]

lld/ELF/Arch/PPC64.cpp

347

While I agree that it is kind of odd to essentially reverse the positions of the primary and extended opcodes, I don't really follow what the details of your proposed update are.

How in your proposal does LDU go from 0xe8000001 to 0x7c000000?
I think that any proposal that puts the primary and secondary opcode in the same field is problematic.

How about keeping the bits where they are for DS and DQ form instructions that have extended opcodes. So lets take primary opcode 58 (LD, LDU, LWA):

LD  = 0xe8000000
LDU = 0xe8000001
LWA = 0xe8000002

Then in this function, all DS-Form (PO in { 57, 58, 61, 62 }) would be converted to a PPCInsn simply as encoding & 0xfc000003.

For the two versions of DQ-Form, we would have:
PO == 56 (only LQ) compute as encoding & 0xfc000000
PO == 61 compute as encoding & 0xfc000007
PO == 6 compute as encoding & 0xfc00000f

How does that sound?

382

Sorry, I should probably not use an extended mnemonic here.
The pla 3, 1000 is just paddi 3, 0, 1000, 1

lld/ELF/Relocations.h

99 ↗

(On Diff #283464)

Should we drop the 'REL34' in the Expr? Its not really important how many bits it represents, and I think the REL is implied by 'PC' in R_RELAX_GOT_PC.

I am definitely OK with this.

Also, should it be added to isRelExpr in Relocations.cpp?

This is just an omission on my part as I didn't know that existed. I'll add it.

[nemanjai]

lld/ELF/Relocations.h

99 ↗

(On Diff #283464)

Just to be clear, the name you are suggesting is R_PPC64_RELAX_GOT_PC, correct? I don't imagine you would like me to drop PPC64 since this is specific to this target.

[sfertile]

lld/ELF/Arch/PPC64.cpp

347

Sorry, I should have proofread my comment. The third one was suppsoed to be LDUX instead of `LDU again.

Your suggestion sounds perfect.

382

Thanks, I'm not that familiar with the new prefixed instructions yet so I didn't realize that was a paddi.

lld/ELF/Relocations.h

99 ↗

(On Diff #283464)

Yep, thats perfect.

[nemanjai]

Cleaned up the definitions of instructions and addressed other minor comments.

[nemanjai]

It is incorrect to relax this relocation if it is on a paddi. Bail out from the optimization if the relocation is on anything but a pld.

[sfertile]

lld/ELF/Arch/PPC64.cpp

75

This helper should return true for any 4-byte load/store instruction that is optimizable as part of a pc-rel access sequence? If so a better name would be isPCRelOptimizable or something along those lines.

lld/ELF/Arch/PPCInsns.def

11 ↗

(On Diff #284974)

This still isn't really the form of a .def file.

1. The enum values are supposed to be defined elsewhere, and the def file is included places where those definitions are visible.
2. I though we agreed to use the encodings directly as the enum values in our previous discussion. So LBZ would be 0x88000000 not 34.
3. We should have 2 distinct enum types, 1 for the non-prefixed instructions (which use an underlying 4 byte integral type) and the 1 for the prefixed instructions which uses an 8-byte type.

Then we should include the 4-byte instruction, the prefixed instruction it maps to, and the operand mask in the macro:
PCREL_OPT(Instruction, Prefixed_Equivalent, Operand_Mask)

Ex:

PCREL_OPT(LBZ, PLBZ, OPC_AND_RST)

And the helpers are implemented by defining the macro. For example to implement getPCRelativeForm:

switch(arg)
{
default:
  return NOINSN;
#define PCREL_OPT(Encoding, Pcrel_Encoding, Op_mask) case Encoding: return Pcrel_Encoding;
#include PPCInsns.def
#undef PCREL_OPT
}

Similarly:
For checkPPCInsn

switch(Encoding) 
{
default return false;
 #define PCREL_OPT(Encoding, Pcrel_Encoding, Op_mask) case Encoding: return true;
#include PPCInsns.def
#undef PCREL_OPT
}

ditto for getInsnMask

[nemanjai]

lld/ELF/Arch/PPC64.cpp

75

Not really. This is meant to check whether the underlying value is one of the enumerators or some value outside of the enumeration.
For example:
checkPPCinsn(static_cast<PPCInsn>(0x6100000A4000000) == true since it is PLWA
while
checkPPCinsn(static_cast<PPCInsn>(0x6100000A400ABCD) == false because it is not the value of any enumerator.

lld/ELF/Arch/PPCInsns.def

11 ↗

(On Diff #284974)

1. I don't think this is true. There are plenty of examples where the enumerators are specified in a .def file. For example include/llvm/IR/Instruction.def. I prefer to leave the defs in the .def file.
2. This is just a bit of miscommunication. I thought we were only talking about instructions for which we need the extended opcode to disambiguate.
3. I am not sure how this improves anything, but sure - since I am indifferent and you have a preference, I'll go with your preference.

[nemanjai]

Split the instruction enums into "Legacy" and "Prefixed" and use the .def file only for functions that access the enums as it simplifies the preprocessor logic.

[stefanp]

This patch makes sense to me.
I have a question about the access instruction but I don't think we should worry about it now.
LGTM!

lld/ELF/Arch/PPC64.cpp

383

Is it possible to have:

paddi 3, 0, 1000, 1
plwz 3, 20(2)

Where both instructions are prefixed.
I assume probably not (clang won't generate it?) but I figured it is worth asking.

513

I guess if the access instruction is already a prefixed instruction there won't be an equivalent PC Relative form of it and we will produce an error here.

[NeHuang]

Overall the patch looks good to me. I only have two questions and a clang-format nit which can be resolved before committing the code.

lld/ELF/Arch/PPC64.cpp

490

nit: clang-format, this can be resolved before committing the changes.

1139

I have two questions regarding void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) in lld/ELF/Arch/PCC64cpp line 619, where had similar check added as below:

case R_PPC64_GOT_PCREL34: {
    // Clear the first 8 bits of the prefix and the first 6 bits of the
...
    if ((insn & 0xfc000000) != 0xe4000000)
      error ("expected a 'pld' for got-indirect to pc-relative relaxing");
...

1. Did it catch the case that paddi instruction with R_PPC64_GOT_PCREL34 emitted from compiler side when it tried to optimize it?
2. After adding the new check here, does it make sense to remove the same check in PPC64::relaxGot?

[nemanjai]

lld/ELF/Arch/PPC64.cpp

383

At this point, it should not be possible (plus it would be a bad thing if it happened since we'd only look at a part of the instruction and part of the displacement).
We bail out before the call to this if we don't have a prefixed version of the instruction (which you already observed below).

490

Not sure what you mean, here. I ran clang-format on the patch and the pre-commit check didn't complain about the formatting.

513

Right, if the access instruction is already prefixed, we'd be looking at the prefix and not the instruction.

1139

1. This check was initially missing so we didn't know that we were mis-optimizing this.
2. I suppose it could be removed, but it is there defensively because if we ever get something other than a pld there, it is guaranteed that the resulting executable will be broken. I chose to go with an error there rather than an assert because it is crucial to fail in such a situation even if we build without asserts.

[NeHuang]

lld/ELF/Arch/PPC64.cpp

490

Yeah, the clang-format pre-check warning is gone after I refresh the page. It could be an outdated message.

[sfertile]

I believe we can have the optimization relocation on a code sequence like:

paddi ra, sym@pcrel
load/store rt, offset(ra)

If so we should have a test showing we relocate it properly even if we don't optimize it yet.

[nemanjai]

In D84360#2215915, @sfertile wrote:

I believe we can have the optimization relocation on a code sequence like:

paddi ra, sym@pcrel
load/store rt, offset(ra)

If so we should have a test showing we relocate it properly even if we don't optimize it yet.

But that's what check_LD_STD_W_PADDI does. Do you mean that I should add checks for the actual values?

[sfertile]

In D84360#2215944, @nemanjai wrote:

But that's what check_LD_STD_W_PADDI does. Do you mean that I should add checks for the actual values?

check_LD_STD_W_PADDI uses paddi referencing the got-entry of the symbol (sym@got@pcrel), My suggestion is for referencing a symbol pcrel (sym@pcrel) combined with a load/store with offset.

lld/ELF/Arch/PPC64.cpp

enum XFormOpcd {
   LDX = 21,
   STBX = 215,
   STHX = 407,
   STWX = 151,
   STDX = 149,
   ADD = 266,
 };
 
 enum DFormOpcd {
-  LBZ = 34,
+  /* Defined below in the PPC enum so they can be used for mapping legacy
+     instructions to pc-relative instructions.
+  LBZ = 34
+  LHZ = 40
+  LWZ = 32
+  LD = 58
+  STB = 38
+  STH = 44
+  STW = 36
+  STD = 62
+  */
   LBZU = 35,
-  LHZ = 40,
   LHZU = 41,
   LHAU = 43,
-  LWZ = 32,
   LWZU = 33,
   LFSU = 49,
-  LD = 58,
   LFDU = 51,
-  STB = 38,
   STBU = 39,
-  STH = 44,
   STHU = 45,
-  STW = 36,
   STWU = 37,
   STFSU = 53,
   STFDU = 55,
-  STD = 62,
   ADDI = 14
 };
 
+// Extracts the 'PO' field of an instruction encoding.
+static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); }
+
+#define PPC_LEGACY_TO_PREFIXED_LINKER
+#include "llvm/Target/PPCLegacyToPCRelMap.def"
+
 uint64_t elf::getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
   // the .got.
   uint64_t tocVA = in.got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
   // thus permitting a full 64 Kbytes segment. Note that the glibc startup
   // code (crt1.o) assumes that you can get from the TOC base to the

 static uint16_t lo(uint64_t v) { return v; }
 static uint16_t hi(uint64_t v) { return v >> 16; }
 static uint16_t ha(uint64_t v) { return (v + 0x8000) >> 16; }
 static uint16_t higher(uint64_t v) { return v >> 32; }
 static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; }
 static uint16_t highest(uint64_t v) { return v >> 48; }
 static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; }
 
-// Extracts the 'PO' field of an instruction encoding.
-static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); }
-
 static bool isDQFormInstruction(uint32_t encoding) {
   switch (getPrimaryOpCode(encoding)) {
   default:
     return false;
+  case 6: // Power10 paired loads/stores (lxvp, stxvp).
   case 56:
     // The only instruction with a primary opcode of 56 is `lq`.
     return true;
   case 61:
     // There are both DS and DQ instruction forms with this primary opcode.
     // Namely `lxv` and `stxv` are the DQ-forms that use it.
     // The DS 'XO' bits being set to 01 is restricted to DQ form.
     return (encoding & 3) == 0x1;
   }
 }
 
 static bool isInstructionUpdateForm(uint32_t encoding) {
   switch (getPrimaryOpCode(encoding)) {
case STD:
     return (encoding & 3) == 1;
   }
 }
 
 // There are a number of places when we either want to read or write an
 // instruction when handling a half16 relocation type. On big-endian the buffer
 // pointer is pointing into the middle of the word we want to extract, and on
 // little-endian it is pointing to the start of the word. These 2 helpers are to
 // simplify reading and writing in that context.
 static void writeFromHalf16(uint8_t *loc, uint32_t insn) {
   write32(config->isLE ? loc : loc - 2, insn);
 }
 
 static uint32_t readFromHalf16(const uint8_t *loc) {
   return read32(config->isLE ? loc : loc - 2);
 }
 
 static uint64_t readPrefixedInstruction(const uint8_t *loc) {
case R_PPC64_TOC16_LO_DS: {
     // "addi reg, 2, var@toc".
     uint32_t insn = readFromHalf16(loc);
     if (getPrimaryOpCode(insn) != LD)
       error("expected a 'ld' for got-indirect to toc-relative relaxing");
     writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000);
     relocateNoSym(loc, R_PPC64_TOC16_LO, val);
     break;
   }
+  case R_PPC64_GOT_PCREL34: {
+    uint64_t insn = readPrefixedInstruction(loc);
+
+    // Clear the first 8 bits of the prefix and the first 6 bits of the
+    // instruction (the primary opcode).
+    insn &= ~0xFF000000FC000000lu;
+
+    // Replace the cleared bits with the values for PADDI (0x600000038000000);
+    insn |= 0x600000038000000lu;
+    writePrefixedInstruction(loc, insn);
+    relocate(loc, rel, val);
+    break;
+  }
+  case R_PPC64_PCREL_OPT: {
+    // We can only relax this if the R_PPC64_GOT_PCREL34 at this offset can
+    // be relaxed. The eligibility for the relaxation needs to be determined
+    // on that relocation since this one does not relocate a symbol.
+    uint64_t insn = readPrefixedInstruction(loc);
+    uint32_t accessInsn = read32(loc + rel.addend);
+    uint64_t pcRelInsn = getPCRelativeForm(accessInsn);
+
+    // This error is not necessary for correctness but is emitted for now
+    // to ensure we don't miss these opportunities in real code. It can be
+    // removed at a later date.
+    if (pcRelInsn == -1lu) {
+      error("unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x" +
+            Twine::utohexstr(accessInsn));
+      break;
+    }
+
+    // Convert the PADDI to the prefixed version of accessInsn and convert
+    // accessInsn to a nop.
+    uint64_t dispOnly = insn & 0x0003ffff0000ffff;
+    uint64_t finalInsn = dispOnly | pcRelInsn;
+    writePrefixedInstruction(loc, finalInsn);
+    write32(loc + rel.addend, 0x60000000); // nop accessInsn.
+    break;
+  }
   default:
     llvm_unreachable("unexpected relocation type");
   }
 }
 
 void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
                            uint64_t val) const {
   // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_GOT16_LO_DS:
     return R_GOT_OFF;
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
     return R_GOTREL;
   case R_PPC64_GOT_PCREL34:
+  case R_PPC64_PCREL_OPT:
     return R_GOT_PC;
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_LO_DS:
     return config->tocOptimize ? R_PPC64_RELAX_TOC : R_GOTREL;
   case R_PPC64_TOC:
     return R_PPC64_TOCBASE;
   case R_PPC64_REL14:
   case R_PPC64_REL24:
if (type == R_PPC64_REL14)
     return isInt<16>(offset);
   if (type == R_PPC64_REL24 || type == R_PPC64_REL24_NOTOC)
     return isInt<26>(offset);
   llvm_unreachable("unsupported relocation type used in branch");
 }
 
 RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data,
                                RelExpr expr) const {
+  if (type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT)
+    return R_RELAX_GOT_PC;
   if (expr == R_RELAX_TLS_GD_TO_IE)
     return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
   if (expr == R_RELAX_TLS_LD_TO_LE)
     return R_RELAX_TLS_LD_TO_LE_ABS;
   return expr;
 }
 
 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
 // The general dynamic code sequence for a global `x` uses 4 instructions.
 // Instruction                    Relocation                Symbol
 // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
 // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x

lld/ELF/InputSection.cpp

else if (sec->areRelocsRela)
     sec->relocateNonAlloc<ELFT>(buf, sec->template relas<ELFT>());
   else
     sec->relocateNonAlloc<ELFT>(buf, sec->template rels<ELFT>());
 }
 
 void InputSectionBase::relocateAlloc(uint8_t *buf, uint8_t *bufEnd) {
   assert(flags & SHF_ALLOC);
   const unsigned bits = config->wordsize * 8;
+  uint64_t lastPPCRelaxedRelocOff = -1lu;
 
   for (const Relocation &rel : relocations) {
     if (rel.expr == R_NONE)
       continue;
     uint64_t offset = rel.offset;
     if (auto *sec = dyn_cast<InputSection>(this))
       offset += sec->outSecOff;
     uint8_t *bufLoc = buf + offset;
     RelType type = rel.type;
 
     uint64_t addrLoc = getOutputSection()->addr + offset;
     RelExpr expr = rel.expr;
     uint64_t targetVA = SignExtend64(
         getRelocTargetVA(file, type, rel.addend, addrLoc, *rel.sym, expr),
         bits);
 
     switch (expr) {
     case R_RELAX_GOT_PC:
-    case R_RELAX_GOT_PC_NOPIC:
+    case R_RELAX_GOT_PC_NOPIC: {
+      // The R_PPC64_PCREL_OPT relocation must appear immediately after
+      // R_PPC64_GOT_PCREL34 in the relocations table at the same offset.
+      // We can only relax R_PPC64_PCREL_OPT if we have also relaxed
+      // the associated R_PPC64_GOT_PCREL34 since only the latter has an
+      // associated symbol. So save the offset when relaxing R_PPC64_GOT_PCREL34
+      // and only relax the other if the saved offset matches.
+      if (type == R_PPC64_GOT_PCREL34)
+        lastPPCRelaxedRelocOff = offset;
+      if (type == R_PPC64_PCREL_OPT && offset != lastPPCRelaxedRelocOff)
+        break;
       target->relaxGot(bufLoc, rel, targetVA);
       break;
+    }
     case R_PPC64_RELAX_TOC:
       // rel.sym refers to the STT_SECTION symbol associated to the .toc input
       // section. If an R_PPC64_TOC16_LO (.toc + addend) references the TOC
       // entry, there may be R_PPC64_TOC16_HA not paired with
       // R_PPC64_TOC16_LO_DS. Don't relax. This loses some relaxation
       // opportunities but is safe.
       if (ppc64noTocRelax.count({rel.sym, rel.addend}) ||
           !tryRelaxPPC64TocIndirection(rel, bufLoc))

llvm/include/llvm/Target/PPCLegacyToPCRelMap.def

+/* This file defines a mapping between legacy instructions and their
+   PC-relative prefixed versions. It has two uses:
+   1. In the compiler, to tell the compiler for which instructions
+      it is allowed to emit the R_PPC64_PCREL_OPT relocation.
+   2. In LLD, to provide the encoding for the PC-relative prefixed
+      version when given the legacy instruction encoding.
+
+   The way this file differentiates between the two is with two macros:
+   PPC_LEGACY_TO_PREFIXED_COMPILER
+   PPC_LEGACY_TO_PREFIXED_LINKER
+
+   Since the linker is just looking at instruction encodings, there is
+   an inevitable amount of bit manipulation here that can be difficult to
+   follow. While a significant amount of effort has gone into documenting
+   the various values and bit positions, the definitive source for instruction
+   encodings is ISA3.1. The reader is encouraged to reference the ISA that can
+   be found at:
+
+   https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
+*/
+#if (!defined PPC_LEGACY_TO_PREFIXED_COMPILER) &&                              \
+    (!defined PPC_LEGACY_TO_PREFIXED_LINKER)
+#error "Need to define PPC_LEGACY_TO_PREFIXED_{COMPILER|LINKER}"
+#endif
+#ifdef PPC_LEGACY_TO_PREFIXED_LINKER
+// For the linker, the enumerators are primary opcodes for the most part.
+// There are some instructions that share primary opcodes. For those, we
+// set the extended opcode field that differentiates them as the most
+// significant bits. For example, LWA and LD share a primary opcode. What
+// differentiates them is the extended opcode field (two least significant
+// bits of the encoding). LWA is 0x10 and LD is 0x0. So in order for the
+// two instructions to have a unique enumerator value and be mapped
+// to the correct prefixed instructions, we shift those values to the
+// most significant bits and or them with the primary opcode.
+enum PPC : uint64_t {
+  // Loads
+  PREFIX_MLS = 0x0610000000000000lu,
+  PREFIX_8LS = 0x0410000000000000lu,
+  LBZ = 34,
+  PLBZpc = PREFIX_MLS, // Prefix only.
+  LBZ8 = 34,
+  PLBZ8pc = PREFIX_MLS, // Prefix only.
+  LHZ = 40,
+  PLHZpc = PREFIX_MLS, // Prefix only.
+  LHZ8 = 40,
+  PLHZ8pc = PREFIX_MLS, // Prefix only.
+  LWZ = 32,
+  PLWZpc = PREFIX_MLS, // Prefix only.
+  LWZ8 = 32,
+  PLWZ8pc = PREFIX_MLS, // Prefix only.
+  LHA = 42,
+  PLHApc = PREFIX_MLS, // Prefix only.
+  LHA8 = 42,
+  PLHA8pc = PREFIX_MLS,               // Prefix only.
+  LWA = 58 | 0x80000000,              // (Encoding & 0x3) << 30.
+  PLWApc = PREFIX_8LS | 0xA4000000lu, // Prefix | Primary opc.
+  LD = 58 | 0x0,                      // (Encoding & 0x3) << 30.
+  PLDpc = PREFIX_8LS | 0xE4000000lu,  // Prefix | Primary opc.
+  LFS = 48,
+  PLFSpc = PREFIX_MLS,                  // Prefix only.
+  LXSSP = 57 | 0xC0000000,              // (Encoding & 0x3) << 30.
+  PLXSSPpc = PREFIX_8LS | 0xAC000000lu, // Prefix | Primary opc.
+  LFD = 50,
+  PLFDpc = PREFIX_MLS,                 // Prefix only.
+  LXSD = 57 | 0x80000000,              // (Encoding & 0x3) << 30.
+  PLXSDpc = PREFIX_8LS | 0xA8000000lu, // Prefix | Primary opc.
+  LXV = 61 | 0x20000000,               // (Encoding & 0x7) << 29.
+  PLXVpc = PREFIX_8LS | 0xC8000000lu,  // Prefix | Primary opc.
+  LXVP = 6 | 0x0,                      // (Encoding & 0xF) << 28.
+  PLXVPpc = PREFIX_8LS | 0xE8000000lu, // Prefix | Primary opc.
+  DFLOADf32 = 48,
+  DFLOADf64 = 50,
+
+  // Stores
+  STB = 38,
+  PSTBpc = PREFIX_MLS, // Prefix only.
+  STB8 = 38,
+  PSTB8pc = PREFIX_MLS, // Prefix only.
+  STH = 44,
+  PSTHpc = PREFIX_MLS, // Prefix only.
+  STH8 = 44,
+  PSTH8pc = PREFIX_MLS, // Prefix only.
+  STW = 36,
+  PSTWpc = PREFIX_MLS, // Prefix only.
+  STW8 = 36,
+  PSTW8pc = PREFIX_MLS, // Prefix only.
+  STD = 62,
+  PSTDpc = PREFIX_8LS | 0xF4000000lu, // Prefix | Primary opc.
+  STFS = 52,
+  PSTFSpc = PREFIX_MLS,                  // Prefix only.
+  STXSSP = 61 | 0xC0000000,              // (Encoding & 0x3) << 30.
+  PSTXSSPpc = PREFIX_8LS | 0xBC000000lu, // Prefix | Primary opc.
+  STFD = 54,
+  PSTFDpc = PREFIX_MLS,                 // Prefix only.
+  STXSD = 61 | 0x80000000,              // (Encoding & 0x3) << 30.
+  PSTXSDpc = PREFIX_8LS | 0xB8000000lu, // Prefix | Primary opc.
+  STXV = 61 | 0xA0000000,               // (Encoding & 0x7) << 29.
+  PSTXVpc = PREFIX_8LS | 0xD8000000lu,  // Prefix | Primary opc.
+  STXVP = 6 | 0x10000000,               // (Encoding & 0xF) << 28.
+  PSTXVPpc = PREFIX_8LS | 0xF8000000lu, // Prefix | Primary opc.
+  DFSTOREf32 = 52,
+  DFSTOREf64 = 54
+};
+
+enum Mask : uint64_t {
+  OPC_AND_RST = 0xFFE00000, // Primary opc (0-5) and R[ST] (6-10).
+  ONLY_RST = 0x3E00000,     // [RS]T (6-10).
+  ST_STX28_TO5 = 0x3E00000, // S/T (6-10) - The [S/T]X bit moves from 28 to 5.
+};
+static const uint64_t InstrMasks[][2] = {
+    // Loads.
+    {PPC::LBZ, OPC_AND_RST},
+    {PPC::LHZ, OPC_AND_RST},
+    {PPC::LWZ, OPC_AND_RST},
+    {PPC::LHA, OPC_AND_RST},
+    {PPC::LWA, ONLY_RST},
+    {PPC::LD, ONLY_RST},
+    {PPC::LFS, OPC_AND_RST},
+    {PPC::LXSSP, ONLY_RST},
+    {PPC::LFD, OPC_AND_RST},
+    {PPC::LXSD, ONLY_RST},
+    {PPC::LXV, ST_STX28_TO5},
+    {PPC::LXVP, ONLY_RST},
+    // Stores.
+    {PPC::STB, OPC_AND_RST},
+    {PPC::STH, OPC_AND_RST},
+    {PPC::STW, OPC_AND_RST},
+    {PPC::STD, ONLY_RST},
+    {PPC::STFS, OPC_AND_RST},
+    {PPC::STXSSP, ONLY_RST},
+    {PPC::STFD, OPC_AND_RST},
+    {PPC::STXSD, ONLY_RST},
+    {PPC::STXV, ST_STX28_TO5},
+    {PPC::STXVP, ONLY_RST}};
+#endif
+
+/*******************************************************************************
+ * The interface between the compiler and the linker is the following table.
+ * It contains the mapping between the legacy instructions and their
+ * pc-relative forms. When support for a new such instruction is added to the
+ * compiler, it needs to be added to this table if the compiler will use this
+ * instruction as a target of the R_PPC64_PCREL_OPT relocation. If this is not
+ * done, the linker will not be able to optimize the instruction.
+ ******************************************************************************/
+static const uint64_t Map[][2] = {
+    // Loads.
+    {PPC::LBZ, PPC::PLBZpc},
+    {PPC::LBZ8, PPC::PLBZ8pc},
+    {PPC::LHZ, PPC::PLHZpc},
+    {PPC::LHZ8, PPC::PLHZ8pc},
+    {PPC::LWZ, PPC::PLWZpc},
+    {PPC::LWZ8, PPC::PLWZ8pc},
+    {PPC::LHA, PPC::PLHApc},
+    {PPC::LHA8, PPC::PLHA8pc},
+    {PPC::LWA, PPC::PLWApc},
+    {PPC::LD, PPC::PLDpc},
+    {PPC::LFS, PPC::PLFSpc},
+    {PPC::LXSSP, PPC::PLXSSPpc},
+    {PPC::LFD, PPC::PLFDpc},
+    {PPC::LXSD, PPC::PLXSDpc},
+    {PPC::LXV, PPC::PLXVpc},
+// FIXME: compiler support for paired memory operations will be added soon.
+//    {PPC::LXVP, PPC::PLXVPpc},
+    {PPC::DFLOADf32, PPC::PLFSpc},
+    {PPC::DFLOADf64, PPC::PLFDpc},
+
+    // Stores.
+    {PPC::STB, PPC::PSTBpc},
+    {PPC::STB8, PPC::PSTB8pc},
+    {PPC::STH, PPC::PSTHpc},
+    {PPC::STH8, PPC::PSTH8pc},
+    {PPC::STW, PPC::PSTWpc},
+    {PPC::STW8, PPC::PSTW8pc},
+    {PPC::STD, PPC::PSTDpc},
+    {PPC::STFS, PPC::PSTFSpc},
+    {PPC::STXSSP, PPC::PSTXSSPpc},
+    {PPC::STFD, PPC::PLFSpc},
+    {PPC::STXSD, PPC::PSTXSDpc},
+    {PPC::STXV, PPC::PSTXVpc},
+// FIXME: compiler support for paired memory operations will be added soon.
+//    {PPC::STXVP, PPC::PSTXVPpc},
+    {PPC::DFSTOREf32, PPC::PSTFSpc},
+    {PPC::DFSTOREf64, PPC::PSTFDpc}};
+
+static unsigned getInstrMapIdx(unsigned Opc) {
+  for (unsigned i = 0; i < llvm::array_lengthof(Map); i++)
+    if (Opc == Map[i][0])
+      return i;
+  return -1u;
+}
+
+#ifdef PPC_LEGACY_TO_PREFIXED_COMPILER
+// For the compiler, we only care if the opcode has an entry in the map.
+static bool hasPCRelativeForm(unsigned Opc) {
+  return getInstrMapIdx(Opc) != -1u;
+}
+
+#else
+// For the linker, we need to be able to replace a legacy instruction with a
+// PC-Relative instruction.
+static unsigned getInstrMaskIdx(unsigned Opc) {
+  for (unsigned i = 0; i < llvm::array_lengthof(Map); i++)
+    if (Opc == InstrMasks[i][0])
+      return i;
+  return -1u;
+}
+
+// Returns the opcode from the PPC enumeration above, accounting for adjustments
+// for instructions that share primary opcodes.
+static uint64_t getAdjustedOpc(unsigned Encoding) {
+  uint64_t Opc = getPrimaryOpCode(Encoding);
+
+  // If the primary opcode is shared between multiple instructions, we need to
+  // fix it up to match the actual instruction we are after.
+
+  // For DQ-Form vector instrs, the two least significant bits are 01 and the
+  // field that differentiates them is 3 bits wide.
+  if (Opc == 61 && (Encoding & 0x3) == 0x1) // LXV/STXV.
+    Opc |= (Encoding & 0x7) << 29;
+
+  // For DS-Form instrs, there are 3 different primary opcodes and the two
+  // least significant bits differentiate instrs that share a PO.
+  else if (Opc == 58 || Opc == 57 || Opc == 61)
+    Opc |= (Encoding & 0x3) << 30;
+
+  // Paired loads and stores from ISA3.1 use the 4 least significant bits to
+  // differentiate.
+  else if (Opc == 6)
+    Opc |= (Encoding & 0xf) << 28;
+  return Opc;
+}
+
+// Given the encoding of a legacy instruction, returns its prefixed PC-relative
+// form with all the displacement bits cleared. The caller is to or this with
+// the displacement bits.
+static uint64_t getPCRelativeForm(unsigned Encoding) {
+  uint64_t Opc = getAdjustedOpc(Encoding);
+  unsigned InstrIdx = getInstrMapIdx(Opc);
+  unsigned MaskIdx = getInstrMaskIdx(Opc);
+  if (InstrIdx == -1u || MaskIdx == -1u)
+    return -1lu;
+
+  // The prefixed instruction is computed by masking out bits from the original
+  // instruction and then or-ing that with the prefixed instruction set bits.
+  uint64_t PrefixedInstr = (uint64_t)Encoding & InstrMasks[MaskIdx][1];
+  PrefixedInstr |= Map[InstrIdx][1];
+
+  // If the mask requires moving bit 28 to bit 5, do that now.
+  if (InstrMasks[MaskIdx][1] == ST_STX28_TO5) {
+    uint64_t STX = (Encoding & 0x8) << 23;
+    PrefixedInstr |= STX;
+  }
+  return PrefixedInstr;
+}
+#endif
+#undef PPC_LEGACY_TO_PREFIXED_COMPILER
+#undef PPC_LEGACY_TO_PREFIXED_LINKER

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

STATISTIC(NumFrameOffFoldInPreEmit,
           "Number of folding frame offset by using r+r in pre-emit peephole");
 
 static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
 
 namespace {
 
-static bool hasPCRelativeForm(MachineInstr &Use) {
-  switch (Use.getOpcode()) {
-  default:
-    return false;
-  case PPC::LBZ:
-  case PPC::LBZ8:
-  case PPC::LHA:
-  case PPC::LHA8:
-  case PPC::LHZ:
-  case PPC::LHZ8:
-  case PPC::LWZ:
-  case PPC::LWZ8:
-  case PPC::STB:
-  case PPC::STB8:
-  case PPC::STH:
-  case PPC::STH8:
-  case PPC::STW:
-  case PPC::STW8:
-  case PPC::LD:
-  case PPC::STD:
-  case PPC::LWA:
-  case PPC::LXSD:
-  case PPC::LXSSP:
-  case PPC::LXV:
-  case PPC::STXSD:
-  case PPC::STXSSP:
-  case PPC::STXV:
-  case PPC::LFD:
-  case PPC::LFS:
-  case PPC::STFD:
-  case PPC::STFS:
-  case PPC::DFLOADf32:
-  case PPC::DFLOADf64:
-  case PPC::DFSTOREf32:
-  case PPC::DFSTOREf64:
-    return true;
-  }
-}
+#define PPC_LEGACY_TO_PREFIXED_COMPILER
+#include "llvm/Target/PPCLegacyToPCRelMap.def"
 
   class PPCPreEmitPeephole : public MachineFunctionPass {
   public:
     static char ID;
     PPCPreEmitPeephole() : MachineFunctionPass(ID) {
       initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry());
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
       return MachineFunctionProperties().set(
           MachineFunctionProperties::Property::NoVRegs);
     }
 
     // This function removes any redundant load immediates. It has two level
     // loops - The outer loop finds the load immediates BBI that could be used
     // to replace following redundancy. The inner loop scans instructions that
     // after BBI to find redundancy and update kill/dead flags accordingly. If
     // AfterBBI is the same as BBI, it is redundant, otherwise any instructions
     // that modify the def register of BBI would break the scanning.
     // DeadOrKillToUnset is a pointer to the previous operand that had the
     // kill/dead flag set. It keeps track of the def register of BBI, the use
     // registers of AfterBBIs and the def registers of AfterBBIs.
     bool removeRedundantLIs(MachineBasicBlock &MBB,
                             const TargetRegisterInfo *TRI) {
       LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n";
                  MBB.dump(); dbgs() << "\n");
 
       DenseSet<MachineInstr *> InstrsToErase;
       for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
         // Skip load immediate that is marked to be erased later because it
         // cannot be used to replace any other instructions.
         if (InstrsToErase.find(&*BBI) != InstrsToErase.end())
           continue;
         // Skip non-load immediate.
         unsigned Opc = BBI->getOpcode();
         if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS &&
             Opc != PPC::LIS8)
           continue;
         // Skip load immediate, where the operand is a relocation (e.g., $r3 =
         // LI target-flags(ppc-lo) %const.0).
         if (!BBI->getOperand(1).isImm())
           continue;
         assert(BBI->getOperand(0).isReg() &&
                "Expected a register for the first operand");
 
         LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump(););
 
         Register Reg = BBI->getOperand(0).getReg();
         int64_t Imm = BBI->getOperand(1).getImm();
         MachineOperand *DeadOrKillToUnset = nullptr;
         if (BBI->getOperand(0).isDead()) {
           DeadOrKillToUnset = &BBI->getOperand(0);
           LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset
                             << " from load immediate " << *BBI
                             << " is a unsetting candidate\n");
         }
         // This loop scans instructions after BBI to see if there is any
         // redundant load immediate.
         for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end();
              ++AfterBBI) {
           // Track the operand that kill Reg. We would unset the kill flag of
           // the operand if there is a following redundant load immediate.
           int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
 
           // We can't just clear implicit kills, so if we encounter one, stop
bool removeRedundantLIs(MachineBasicBlock &MBB,
           LLVM_DEBUG(dbgs() << " Remove redundant load immediate: ";
                      AfterBBI->dump());
         }
       }
 
       for (MachineInstr *MI : InstrsToErase) {
         MI->eraseFromParent();
       }
       NumRemovedInPreEmit += InstrsToErase.size();
       return !InstrsToErase.empty();
     }
 
     // Check if this instruction is a PLDpc that is part of a GOT indirect
     // access.
     bool isGOTPLDpc(MachineInstr &Instr) {
       if (Instr.getOpcode() != PPC::PLDpc)
         return false;
 
       // The result must be a register.
       const MachineOperand &LoadedAddressReg = Instr.getOperand(0);
       if (!LoadedAddressReg.isReg())
         return false;
 
       // Make sure that this is a global symbol.
       const MachineOperand &SymbolOp = Instr.getOperand(1);
       if (!SymbolOp.isGlobal())
         return false;
 
       // Finally return true only if the GOT flag is present.
       return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
     }
 
     bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
       MachineFunction *MF = MBB.getParent();
       // Add this linker opt only if we are using PC Relative memops.
       if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls())
         return false;
 
       // Struct to keep track of one def/use pair for a GOT indirect access.
       struct GOTDefUsePair {
         MachineBasicBlock::iterator DefInst;
bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
           CandPairs.push_back(CurrentPair);
           continue;
         }
 
         // We haven't encountered any new PLD instructions, nothing to check.
         if (CandPairs.empty())
           continue;
 
         // Run through the candidate pairs and see if any of the registers
         // defined in the PLD instructions are used by this instruction.
         // Note: the size of CandPairs can change in the loop.
         for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) {
           GOTDefUsePair &Pair = CandPairs[Idx];
           // The instruction does not use or modify this PLD's def reg,
           // ignore it.
           if (!BBI->readsRegister(Pair.DefReg, TRI) &&
               !BBI->modifiesRegister(Pair.DefReg, TRI))
             continue;
 
           // The use needs to be used in the address compuation and not
           // as the register being stored for a store.
-          const MachineOperand *UseOp =
-              hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr;
+          const MachineOperand *UseOp = hasPCRelativeForm(BBI->getOpcode())
+                                            ? &BBI->getOperand(2)
+                                            : nullptr;
 
           // Check for a valid use.
           if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
               UseOp->isUse() && UseOp->isKill()) {
             Pair.UseInst = BBI;
             Pair.UseReg = BBI->getOperand(0).getReg();
             ValidPairs.push_back(Pair);
           }
           CandPairs.erase(CandPairs.begin() + Idx);
         }
       }
 
       // Go through all of the pairs and check for any more valid uses.
       for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) {
         // We shouldn't be here if we don't have a valid pair.
         assert(Pair->UseInst.isValid() && Pair->StillValid &&
                "Kept an invalid def/use pair for GOT PCRel opt");
         // We have found a potential pair. Search through the instructions
         // between the def and the use to see if it is valid to mark this as a
         // linker opt.
         MachineBasicBlock::iterator BBI = Pair->DefInst;
         ++BBI;
         for (; BBI != Pair->UseInst; ++BBI) {
           if (BBI->readsRegister(Pair->UseReg, TRI) ||
               BBI->modifiesRegister(Pair->UseReg, TRI)) {
             Pair->StillValid = false;
             break;
           }
         }
 
         if (!Pair->StillValid)
           continue;
 
         // The load/store instruction that uses the address from the PLD will
         // either use a register (for a store) or define a register (for the
         // load). That register will be added as an implicit def to the PLD
         // and as an implicit use on the second memory op. This is a precaution
         // to prevent future passes from using that register between the two
bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
         MCSymbol *Symbol =
             Context.createTempSymbol(Twine("pcrel"), false, false);
         MachineOperand PCRelLabel =
             MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG);
         Pair->DefInst->addOperand(*MF, PCRelLabel);
         Pair->UseInst->addOperand(*MF, PCRelLabel);
         MadeChange |= true;
       }
       return MadeChange;
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
         // Remove UNENCODED_NOP even when this pass is disabled.
         // This needs to be done unconditionally so we don't emit zeros
         // in the instruction stream.
         SmallVector<MachineInstr *, 4> InstrsToErase;
         for (MachineBasicBlock &MBB : MF)
           for (MachineInstr &MI : MBB)
             if (MI.getOpcode() == PPC::UNENCODED_NOP)
               InstrsToErase.push_back(&MI);
         for (MachineInstr *MI : InstrsToErase)
           MI->eraseFromParent();
         return false;
       }
       bool Changed = false;
       const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
       SmallVector<MachineInstr *, 4> InstrsToErase;
       for (MachineBasicBlock &MBB : MF) {
         Changed |= removeRedundantLIs(MBB, TRI);
         Changed |= addLinkerOpt(MBB, TRI);
         for (MachineInstr &MI : MBB) {
           unsigned Opc = MI.getOpcode();
           if (Opc == PPC::UNENCODED_NOP) {
             InstrsToErase.push_back(&MI);
             continue;
           }
           // Detect self copies - these can result from running AADB.
           if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
             const MCInstrDesc &MCID = TII->get(Opc);
             if (MCID.getNumOperands() == 3 &&
                 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
                 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
               NumberOfSelfCopies++;
               LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
               LLVM_DEBUG(MI.dump());
               InstrsToErase.push_back(&MI);
               continue;
             }
             else if (MCID.getNumOperands() == 2 &&
                      MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
               NumberOfSelfCopies++;
               LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
               LLVM_DEBUG(MI.dump());
               InstrsToErase.push_back(&MI);
               continue;
             }
           }
           MachineInstr *DefMIToErase = nullptr;
           if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
             Changed = true;
             NumRRConvertedInPreEmit++;
             LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
             LLVM_DEBUG(MI.dump());
             if (DefMIToErase) {
               InstrsToErase.push_back(DefMIToErase);
             }
           }
           if (TII->foldFrameOffset(MI)) {
             Changed = true;
             NumFrameOffFoldInPreEmit++;
             LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: ");
             LLVM_DEBUG(MI.dump());
           }
         }
 
         // Eliminate conditional branch based on a constant CR bit by
         // CRSET or CRUNSET. We eliminate the conditional branch or
         // convert it into an unconditional branch. Also, if the CR bit
         // is not used by other instructions, we eliminate CRSET as well.
         auto I = MBB.getFirstInstrTerminator();
         if (I == MBB.instr_end())
           continue;
         MachineInstr *Br = &*I;
         if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn)
           continue;
         MachineInstr *CRSetMI = nullptr;
         Register CRBit = Br->getOperand(0).getReg();
         unsigned CRReg = getCRFromCRBit(CRBit);
         bool SeenUse = false;
         MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend();
         for (It++; It != Er; It++) {
           if (It->modifiesRegister(CRBit, TRI)) {
             if ((It->getOpcode() == PPC::CRUNSET ||
                  It->getOpcode() == PPC::CRSET) &&
                 It->getOperand(0).getReg() == CRBit)
               CRSetMI = &*It;
             break;
           }
           if (It->readsRegister(CRBit, TRI))
             SeenUse = true;
         }
         if (!CRSetMI) continue;
 
         unsigned CRSetOp = CRSetMI->getOpcode();
         if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) ||
             (Br->getOpcode() == PPC::BC  && CRSetOp == PPC::CRUNSET)) {
           // Remove this branch since it cannot be taken.
           InstrsToErase.push_back(Br);
           MBB.removeSuccessor(Br->getOperand(1).getMBB());
         }
bool runOnMachineFunction(MachineFunction &MF) override {
             TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
                               NoCond, Br->getDebugLoc());
           }
           for (auto &Succ : MBB.successors())
             if (Succ != Br->getOperand(1).getMBB()) {
               MBB.removeSuccessor(Succ);
               break;
             }
         }
 
         // If the CRBit is not used by another instruction, we can eliminate
         // CRSET/CRUNSET instruction.
         if (!SeenUse) {
           // We need to check use of the CRBit in successors.
           for (auto &SuccMBB : MBB.successors())
             if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) {
               SeenUse = true;
               break;
             }
           if (!SeenUse)
             InstrsToErase.push_back(CRSetMI);
         }
       }
       for (MachineInstr *MI : InstrsToErase) {
         LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: ");
         LLVM_DEBUG(MI->dump());
         MI->eraseFromParent();
         NumRemovedInPreEmit++;
       }
       return Changed;
     }
   };
 }
 
 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole",
                 false, false)
 char PPCPreEmitPeephole::ID = 0;
 
 FunctionPass *llvm::createPPCPreEmitPeepholePass() {
   return new PPCPreEmitPeephole();
 }