[CodeGen] Don't combine extract + concat vectors with non-legal types

[stuij]

Summary

The following combine currently breaks in the DAGCombiner:

extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x
   -> extract_vector_elt a, x

This happens because after we have combined these nodes we have inserted nodes
that use individual instances of the vector element type. In the above example
i16. However this isn't a legal type on all backends, and when the combining pass calls
the legalizer it breaks as it expects types to already be legal. The type legalizer has
already been run, and running it again would make a mess of the nodes.

In the example code at least, the generated code is still efficient after the change.

[miyuki]

LGTM. Please wait until Friday before committing, so that others have a chance to share their objections.

[lebedev.ri]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

17817–17818

!LegalTyepes || TLI.isTypeLegal(

[stuij]

addressed review comment

[stuij]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

17817–17818

Thanks. Fixed this.

[lebedev.ri]

Thanks

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (VecOp.getOpcode() == ISD::BITCAST) {
 
       VecOp = VecOp.getOperand(0);
     }
     if (ISD::isNormalLoad(VecOp.getNode())) {
       LN0 = cast<LoadSDNode>(VecOp);
       Elt = (Idx < (int)NumElts) ? Idx : Idx - (int)NumElts;
       Index = DAG.getConstant(Elt, DL, Index.getValueType());
     }
-  } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS &&
-             !BCNumEltsChanged && VecVT.getVectorElementType() == ScalarVT) {
+  } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged &&
+             VecVT.getVectorElementType() == ScalarVT &&
+             TLI.isTypeLegal(
+                 VecOp.getOperand(0).getValueType().getVectorElementType())) {
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0
     //      -> extract_vector_elt a, 0
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1
     //      -> extract_vector_elt a, 1
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 2
     //      -> extract_vector_elt b, 0
     // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 3
     //      -> extract_vector_elt b, 1

llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll

+; RUN: llc -asm-verbose=0 -mtriple aarch64-arm-none-eabi < %s | FileCheck %s
+
+; The following code previously broke in the DAGCombiner. Specifically, trying to combine:
+; extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x
+;   -> extract_vector_elt a, x
+
+define half @test_combine_extract_concat_vectors(<4 x i16> %a) nounwind {
+entry:
+  %0 = shufflevector <4 x i16> %a, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %1 = bitcast <8 x i16> %0 to <8 x half>
+  %2 = extractelement <8 x half> %1, i32 3
+  ret half %2
+}
+
+; CHECK-LABEL: test_combine_extract_concat_vectors:
+; CHECK-NEXT: mov h0, v0.h[3]
+; CHECK-NEXT: ret