[RISCV][WIP] Improve RV32 constant materialization

[luismarques]

Summary

D79492 improves the materialization of constants for RV64. For ease of review, I'm splitting out several changes and improvements into separate patches.
This patch addresses RV32. For RV32, LUI/ADDI/LUI+ADDI is already optimal regarding the number of instructions, but we can use alternative sequences for improved compressibility.
Since we don't need the recursive approach of D79492, it's clearer and more efficient to split the two implementations.
For ease of review, this patch contributes only the RV32 improvements to constant materialization, with a split implementation approach.
I'm marking this patch/review as WIP due to the following code quality issues.
In isolation, these constant materialization changes should always be reasonable. Unfortunately, when multiple constants need to be materialized these optimizations can result in worse outcomes, due to how we optimize each constant materialization in isolation. For instance:

x = 0x80000000
y = 0x7FFFFFFF

Before:
x = (LUI 0x80000)
y = (ADDI (LUI 0x80000) -1) = (ADDI x -1)
=> LUI+ADDI

After:
x = (LUI 0x80000)
y = (SRLI (ADDI zero, -1) 1)
=> LUI+ADDI+SRLI

An example of this scenario occurs in copysign-casts.ll.
Another issue is that removing the ADDI from the materialization screws up folding the ADDIs into the load/stores (see fold-addi-loadstore.ll) and the computation of base+offset addresses (see hoist-global-addr-base.ll).
While these issues can be avoided for RV32I, by gating the materialization optimizations to +C, the problem remains for RVC.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

case ISD::Constant: {
     auto ConstNode = cast<ConstantSDNode>(Node);
     if (VT == XLenVT && ConstNode->isNullValue()) {
       SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
                                            RISCV::X0, XLenVT);
       ReplaceNode(Node, New.getNode());
       return;
     }
     int64_t Imm = ConstNode->getSExtValue();
-    if (XLenVT == MVT::i64) {
-      ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));
-      return;
-    }
-    break;
-  }
   case ISD::FrameIndex: {
     SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
     int FI = cast<FrameIndexSDNode>(Node)->getIndex();
     SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
     ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
     return;
   }
   case ISD::SRL: {

llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/MathExtras.h"
 #include <cstdint>
 
 namespace llvm {
 
 namespace RISCVMatInt {
-void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
+static void generateInstSeq32(int32_t Val, InstSeq &Res) {
+  int32_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
+  int32_t Lo12 = SignExtend32<12>(Val);
+
+  // Does the general case require LUI+ADDI, and they aren't both compressed?
+  // If so, first try to materialize the constant using shifts.
+  if (Hi20 && Lo12 && (!isInt<6>(Hi20) || !isInt<6>(Lo12))) {
+    unsigned FirstSet = findFirstSet((uint32_t)Val);
+
+    // Try XXX0* -> ADDI(XXX)+SLLI.
+    int ShiftAmount = FirstSet;
+    if (ShiftAmount > 0) {
+      int32_t AltVal = SignExtend32(Val >> ShiftAmount, 32 - ShiftAmount);
+      if (isInt<12>(AltVal)) {
+        Res.push_back(Inst(RISCV::ADDI, AltVal));
+        Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
+        return;
+      }
+    }
+
+    if (Val > 0) {
+      // Try 0*XXX -> ADDI(XXX1*)+SRLI.
+      int ShiftAmount = countLeadingZeros((uint32_t)Val);
+      int32_t AltVal = (Val << ShiftAmount) | ((1 << ShiftAmount) - 1);
+      if (isInt<12>(AltVal)) {
+        Res.push_back(Inst(RISCV::ADDI, AltVal));
+        Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+        return;
+      }
+
+      // Try 0*XXX -> LUI(XXX)+SRLI.
+      if (isUInt<20>(Val >> FirstSet)) {
+        AltVal = uint32_t(Val << ShiftAmount) >> 12;
+        Res.push_back(Inst(RISCV::LUI, AltVal));
+        Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+        return;
+      }
+    }
+  }
+
+  // Depending on the active bits in the constant, the following
+  // instruction sequences are emitted in the general case:
+  //
+  // Val == 0                          : ADDI
+  // Val[0,12) != 0 && Val[12,32) == 0 : ADDI
+  // Val[0,12) == 0 && Val[12,32) != 0 : LUI
+  // Val[0,32) != 0                    : LUI+ADDI(W)
+
+  if (Hi20)
+    Res.push_back(Inst(RISCV::LUI, Hi20));
+
+  if (Lo12 || Hi20 == 0)
+    Res.push_back(Inst(RISCV::ADDI, Lo12));
+}
+
+static void generateInstSeq64(int64_t Val, InstSeq &Res) {
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
     //
     // v == 0                        : ADDI
     // v[0,12) != 0 && v[12,32) == 0 : ADDI
     // v[0,12) == 0 && v[12,32) != 0 : LUI
     // v[0,32) != 0                  : LUI+ADDI(W)
     int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
     int64_t Lo12 = SignExtend64<12>(Val);
 
     if (Hi20)
       Res.push_back(Inst(RISCV::LUI, Hi20));
 
     if (Lo12 || Hi20 == 0) {
-      unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
+      unsigned AddiOpc = Hi20 ? RISCV::ADDIW : RISCV::ADDI;
       Res.push_back(Inst(AddiOpc, Lo12));
     }
     return;
   }
 
-  assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
-
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
   // while the following ADDI instructions contribute up to 12 bits each.
   //
   // On the first glance, implementing this seems to be possible by simply
   // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
   // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
static void generateInstSeq64(int64_t Val, InstSeq &Res) {
   // fits into 32 bits. The emission of the shifts and additions is subsequently
   // performed when the recursion returns.
 
   int64_t Lo12 = SignExtend64<12>(Val);
   int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
-  generateInstSeq(Hi52, IsRV64, Res);
+  generateInstSeq64(Hi52, Res);
 
   Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(Inst(RISCV::ADDI, Lo12));
 }
 
+void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
+  if (!IsRV64) {
+    assert(isInt<32>(Val));
+    generateInstSeq32(Val, Res);
+  }
+  else
+    generateInstSeq64(Val, Res);
+}
+
 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;
   for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
     InstSeq MatSeq;
     generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq);
     Cost += MatSeq.size();
   }
   return std::max(1, Cost);
 }
 } // namespace RISCVMatInt
 } // namespace llvm

llvm/test/CodeGen/RISCV/alu16.ll

 ; RV64I-NEXT:    ret
   %1 = shl i16 %a, 7
   ret i16 %1
 }
 
 define i16 @srli(i16 %a) nounwind {
 ; RV32I-LABEL: srli:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi a1, a1, -64
+; RV32I-NEXT:    addi a1, zero, 1023
+; RV32I-NEXT:    slli a1, a1, 6
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    srli a0, a0, 6
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: srli:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw a1, a1, -64

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

; RV32I-NEXT:    ret
   %tmp = call i16 @llvm.bswap.i16(i16 %a)
   ret i16 %tmp
 }
 
 define i32 @test_bswap_i32(i32 %a) nounwind {
 ; RV32I-LABEL: test_bswap_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -256
+; RV32I-NEXT:    addi a2, zero, 255
+; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a2, a0, 24
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    slli a2, a0, 8
 ; RV32I-NEXT:    lui a3, 4080
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
   %tmp = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %tmp
 }
 
 define i64 @test_bswap_i64(i64 %a) nounwind {
 ; RV32I-LABEL: test_bswap_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a1, 8
-; RV32I-NEXT:    lui a3, 16
-; RV32I-NEXT:    addi a3, a3, -256
+; RV32I-NEXT:    addi a3, zero, 255
+; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
 ; RV32I-NEXT:    slli a4, a1, 8
 ; RV32I-NEXT:    lui a5, 4080
 ; RV32I-NEXT:    and a4, a4, a5
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    or a1, a1, a4

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

 }
 
 define i32 @caller_small_scalar_ret() nounwind {
 ; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    call callee_small_scalar_ret
-; RV32I-FPELIM-NEXT:    lui a2, 56
-; RV32I-FPELIM-NEXT:    addi a2, a2, 580
+; RV32I-FPELIM-NEXT:    lui a2, 919824
+; RV32I-FPELIM-NEXT:    srli a2, a2, 14
 ; RV32I-FPELIM-NEXT:    xor a1, a1, a2
 ; RV32I-FPELIM-NEXT:    lui a2, 200614
 ; RV32I-FPELIM-NEXT:    addi a2, a2, 647
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a2
 ; RV32I-FPELIM-NEXT:    or a0, a0, a1
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    call callee_small_scalar_ret
-; RV32I-WITHFP-NEXT:    lui a2, 56
-; RV32I-WITHFP-NEXT:    addi a2, a2, 580
+; RV32I-WITHFP-NEXT:    lui a2, 919824
+; RV32I-WITHFP-NEXT:    srli a2, a2, 14
 ; RV32I-WITHFP-NEXT:    xor a1, a1, a2
 ; RV32I-WITHFP-NEXT:    lui a2, 200614
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 647
 ; RV32I-WITHFP-NEXT:    xor a0, a0, a2
 ; RV32I-WITHFP-NEXT:    or a0, a0, a1
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)

llvm/test/CodeGen/RISCV/copysign-casts.ll

 declare double @llvm.copysign.f64(double, double)
 declare float @llvm.copysign.f32(float, float)
 
 define double @fold_promote(double %a, float %b) nounwind {
 ; RV32I-LABEL: fold_promote:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 524288
 ; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    addi a3, a3, -1
+; RV32I-NEXT:    addi a3, zero, -1
+; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, -1
 ; RV64I-NEXT:    slli a2, a2, 63
 ; RV64I-NEXT:    addi a2, a2, -1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    slli a2, a2, 31
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_promote:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a2, fa0
 ; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    and a2, a2, a3
-; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    addi a3, zero, -1
+; RV32IF-NEXT:    srli a3, a3, 1
 ; RV32IF-NEXT:    and a1, a1, a3
 ; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_promote:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fcvt.d.s ft0, fa1
 ; RV32IFD-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_promote:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.d.s ft0, fa1
 ; RV64IFD-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV64IFD-NEXT:    ret
   %c = fpext float %b to double
   %t = call double @llvm.copysign.f64(double %a, double %c)
   ret double %t
 }
 
 define float @fold_demote(float %a, double %b) nounwind {
 ; RV32I-LABEL: fold_demote:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    and a2, a2, a1
-; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    addiw a2, a2, -1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    addi a2, zero, -1

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

; RV64IFD-NEXT:    ret
   ret double %1
 }
 
 declare double @llvm.fabs.f64(double)
 
 define double @fabs(double %a) nounwind {
 ; RV32I-LABEL: fabs:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fabs:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    addi a2, zero, -1
+; RV32IFD-NEXT:    srli a2, a2, 1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    addi a1, a1, -1

 ; do the same even when f64 is legal.
 
 define double @fcopysign_fneg(double %a, double %b) nounwind {
 ; RV32I-LABEL: fcopysign_fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a2, a3
 ; RV32I-NEXT:    lui a3, 524288
 ; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    addi a3, a3, -1
+; RV32I-NEXT:    addi a3, zero, -1
+; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fcopysign_fneg:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)

llvm/test/CodeGen/RISCV/double-intrinsics.ll

; RV64IFD-NEXT:    ret
   ret double %1
 }
 
 declare double @llvm.fabs.f64(double)
 
 define double @fabs_f64(double %a) nounwind {
 ; RV32IFD-LABEL: fabs_f64:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    addi a2, zero, -1
+; RV32IFD-NEXT:    srli a2, a2, 1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
 ; RV64IFD-NEXT:    slli a1, a1, 63
 ; RV64IFD-NEXT:    addi a1, a1, -1

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

 ; RV32F-NEXT:    addi sp, sp, -16
 ; RV32F-NEXT:    sw ra, 12(sp)
 ; RV32F-NEXT:    sw s0, 8(sp)
 ; RV32F-NEXT:    sw s1, 4(sp)
 ; RV32F-NEXT:    mv s0, a1
 ; RV32F-NEXT:    mv s1, a0
 ; RV32F-NEXT:    call __adddf3
 ; RV32F-NEXT:    mv a2, a0
-; RV32F-NEXT:    lui a0, 524288
-; RV32F-NEXT:    addi a0, a0, -1
+; RV32F-NEXT:    addi a0, zero, -1
+; RV32F-NEXT:    srli a0, a0, 1
 ; RV32F-NEXT:    and a3, a1, a0
 ; RV32F-NEXT:    mv a0, s1
 ; RV32F-NEXT:    mv a1, s0
 ; RV32F-NEXT:    call __adddf3
 ; RV32F-NEXT:    lw s1, 4(sp)
 ; RV32F-NEXT:    lw s0, 8(sp)
 ; RV32F-NEXT:    lw ra, 12(sp)
 ; RV32F-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

; RV64IF-NEXT:    ret
   ret float %1
 }
 
 declare float @llvm.fabs.f32(float)
 
 define float @fabs(float %a) nounwind {
 ; RV32I-LABEL: fabs:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    addi a1, zero, -1
+; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fabs:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    addi a1, zero, -1
+; RV32IF-NEXT:    srli a1, a1, 1
 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1

 ; do the same even when f32 is legal.
 
 define float @fcopysign_fneg(float %a, float %b) nounwind {
 ; RV32I-LABEL: fcopysign_fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fcopysign_fneg:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a2, 524288
 ; RV32IF-NEXT:    xor a1, a1, a2

llvm/test/CodeGen/RISCV/float-intrinsics.ll

; RV64IF-NEXT:    ret
   ret float %1
 }
 
 declare float @llvm.fabs.f32(float)
 
 define float @fabs_f32(float %a) nounwind {
 ; RV32IF-LABEL: fabs_f32:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    addi a1, zero, -1
+; RV32IF-NEXT:    srli a1, a1, 1
 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fabs_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a1, 524288
 ; RV64IF-NEXT:    addiw a1, a1, -1
 ; RV64IF-NEXT:    and a0, a0, a1

llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll

 entry:
   %0 = load i64, i64* inttoptr (i32 2040 to i64*)
   ret i64 %0
 }
 
 define i64 @load_cost_overflow() nounwind {
 ; RV32I-LABEL: load_cost_overflow:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    lw a1, -2048(a0)
+; RV32I-NEXT:    addi a0, zero, 1
+; RV32I-NEXT:    slli a0, a0, 11
+; RV32I-NEXT:    lw a1, 0(a0)
 ; RV32I-NEXT:    lw a0, 2044(zero)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_cost_overflow:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    ld a0, 2044(zero)
 ; RV64I-NEXT:    ret
 entry:
   %0 = load i64, i64* inttoptr (i64 2044 to i64*)
   ret i64 %0
 }

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

 ; lui  a1, %hi(g)
 ; addi a1, a0, %lo(g)
 ; lui  a0, 18     ---> offset
 ; addi a0, a0, -160
 ; add  a0, a0, a1  ---> base + offset.
 define i8* @big_offset_neg_addi() nounwind {
 ; CHECK-LABEL: big_offset_neg_addi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(g+73568)
-; CHECK-NEXT:    addi a0, a0, %lo(g+73568)
+; CHECK-NEXT:    lui a0, 588544
+; CHECK-NEXT:    srli a0, a0, 15
+; CHECK-NEXT:    lui a1, %hi(g)
+; CHECK-NEXT:    addi a1, a1, %lo(g)
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 73568)
 }
 
 ; This test checks for the case where the offset is only an LUI.
 ; without peephole this generates:
 ; lui  a0, %hi(g)
 ; addi a0, a0, %lo(g)
 ; lui  a1, 128     ---> offset
 ; add  a0, a0, a1  ---> base + offset.
 define i8* @big_offset_lui_tail() nounwind {
 ; CHECK-LABEL: big_offset_lui_tail:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(g+524288)
 ; CHECK-NEXT:    addi a0, a0, %lo(g+524288)
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 524288)
 }
 
 define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
 ; CHECK-LABEL: big_offset_one_use:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lui a0, %hi(s+16572)
-; CHECK-NEXT:    addi a0, a0, %lo(s+16572)
+; CHECK-NEXT:    lui a0, 530304
+; CHECK-NEXT:    srli a0, a0, 17
+; CHECK-NEXT:    lui a1, %hi(s)
+; CHECK-NEXT:    addi a1, a1, %lo(s)
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ret
 entry:
   ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
 }
 
 define dso_local i32* @small_offset_one_use() local_unnamed_addr nounwind {
 ; CHECK-LABEL: small_offset_one_use:
 ; CHECK:       # %bb.0: # %entry

llvm/test/CodeGen/RISCV/imm.ll

; RV64I-NEXT:    ret
   ret i32 -65536 ; -0x10000
 }
 
 ; This can be materialized with ADDI+SLLI, improving compressibility.
 
 define signext i32 @imm_left_shifted_addi() nounwind {
 ; RV32I-LABEL: imm_left_shifted_addi:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 32
-; RV32I-NEXT:    addi a0, a0, -64
+; RV32I-NEXT:    addi a0, zero, 2047
+; RV32I-NEXT:    slli a0, a0, 6
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_addi:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 32
 ; RV64I-NEXT:    addiw a0, a0, -64
 ; RV64I-NEXT:    ret
   ret i32 131008 ; 0x1FFC0
 }
 
 ; This can be materialized with ADDI+SRLI, improving compressibility.
 
 define signext i32 @imm_right_shifted_addi() nounwind {
 ; RV32I-LABEL: imm_right_shifted_addi:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    addi a0, zero, -1
+; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_addi:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    addiw a0, a0, -1
 ; RV64I-NEXT:    ret
   ret i32 2147483647 ; 0x7FFFFFFF
 }
 
 ; This can be materialized with LUI+SRLI, improving compressibility.
 
 define signext i32 @imm_right_shifted_lui() nounwind {
 ; RV32I-LABEL: imm_right_shifted_lui:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 56
-; RV32I-NEXT:    addi a0, a0, 580
+; RV32I-NEXT:    lui a0, 919824
+; RV32I-NEXT:    srli a0, a0, 14
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 56
 ; RV64I-NEXT:    addiw a0, a0, 580
 ; RV64I-NEXT:    ret
   ret i32 229956 ; 0x38244
; RV64I-NEXT:    ret
   ret i64 17596481011709 ; 0x1000_FFFF_FFFD
 }
 
 ; This constant can be materialized for RV64 with LUI+SRLI+XORI.
 
 define i64 @imm_end_xori_1() nounwind {
 ; RV32I-LABEL: imm_end_xori_1:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 8192
-; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    addi a0, zero, -1
+; RV32I-NEXT:    srli a0, a0, 7
 ; RV32I-NEXT:    lui a1, 917504
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_end_xori_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a0, zero, -1
 ; RV64I-NEXT:    slli a0, a0, 36
 ; RV64I-NEXT:    addi a0, a0, 1

llvm/test/CodeGen/RISCV/large-stack.ll

 ; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -2032
 ; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 2032
 ; RV32I-FPELIM-NEXT:    sw s0, 2028(sp)
 ; RV32I-FPELIM-NEXT:    sw s1, 2024(sp)
 ; RV32I-FPELIM-NEXT:    .cfi_offset s0, -4
 ; RV32I-FPELIM-NEXT:    .cfi_offset s1, -8
-; RV32I-FPELIM-NEXT:    lui a1, 97
-; RV32I-FPELIM-NEXT:    addi a1, a1, 672
+; RV32I-FPELIM-NEXT:    lui a1, 795968
+; RV32I-FPELIM-NEXT:    srli a1, a1, 13
 ; RV32I-FPELIM-NEXT:    sub sp, sp, a1
 ; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 400016
-; RV32I-FPELIM-NEXT:    lui a1, 78
-; RV32I-FPELIM-NEXT:    addi a1, a1, 512
+; RV32I-FPELIM-NEXT:    addi a1, zero, 625
+; RV32I-FPELIM-NEXT:    slli a1, a1, 9
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 8
 ; RV32I-FPELIM-NEXT:    add a1, a2, a1
 ; RV32I-FPELIM-NEXT:    #APP
 ; RV32I-FPELIM-NEXT:    nop
 ; RV32I-FPELIM-NEXT:    #NO_APP
 ; RV32I-FPELIM-NEXT:    sw a0, 0(a1)
 ; RV32I-FPELIM-NEXT:    #APP
 ; RV32I-FPELIM-NEXT:    nop
 ; RV32I-FPELIM-NEXT:    #NO_APP
-; RV32I-FPELIM-NEXT:    lui a0, 97
-; RV32I-FPELIM-NEXT:    addi a0, a0, 672
+; RV32I-FPELIM-NEXT:    lui a0, 795968
+; RV32I-FPELIM-NEXT:    srli a0, a0, 13
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0
 ; RV32I-FPELIM-NEXT:    lw s1, 2024(sp)
 ; RV32I-FPELIM-NEXT:    lw s0, 2028(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 2032
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
 ; RV32I-WITHFP-NEXT:    sw ra, 2028(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 2024(sp)
 ; RV32I-WITHFP-NEXT:    sw s1, 2020(sp)
 ; RV32I-WITHFP-NEXT:    sw s2, 2016(sp)
 ; RV32I-WITHFP-NEXT:    .cfi_offset ra, -4
 ; RV32I-WITHFP-NEXT:    .cfi_offset s0, -8
 ; RV32I-WITHFP-NEXT:    .cfi_offset s1, -12
 ; RV32I-WITHFP-NEXT:    .cfi_offset s2, -16
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa s0, 0
-; RV32I-WITHFP-NEXT:    lui a1, 97
-; RV32I-WITHFP-NEXT:    addi a1, a1, 688
+; RV32I-WITHFP-NEXT:    lui a1, 796000
+; RV32I-WITHFP-NEXT:    srli a1, a1, 13
 ; RV32I-WITHFP-NEXT:    sub sp, sp, a1
-; RV32I-WITHFP-NEXT:    lui a1, 78
-; RV32I-WITHFP-NEXT:    addi a1, a1, 512
+; RV32I-WITHFP-NEXT:    addi a1, zero, 625
+; RV32I-WITHFP-NEXT:    slli a1, a1, 9
 ; RV32I-WITHFP-NEXT:    lui a2, 1048478
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 1388
 ; RV32I-WITHFP-NEXT:    add a2, s0, a2
 ; RV32I-WITHFP-NEXT:    mv a2, a2
 ; RV32I-WITHFP-NEXT:    add a1, a2, a1
 ; RV32I-WITHFP-NEXT:    #APP
 ; RV32I-WITHFP-NEXT:    nop
 ; RV32I-WITHFP-NEXT:    #NO_APP
 ; RV32I-WITHFP-NEXT:    sw a0, 0(a1)
 ; RV32I-WITHFP-NEXT:    #APP
 ; RV32I-WITHFP-NEXT:    nop
 ; RV32I-WITHFP-NEXT:    #NO_APP
-; RV32I-WITHFP-NEXT:    lui a0, 97
-; RV32I-WITHFP-NEXT:    addi a0, a0, 688
+; RV32I-WITHFP-NEXT:    lui a0, 796000
+; RV32I-WITHFP-NEXT:    srli a0, a0, 13
 ; RV32I-WITHFP-NEXT:    add sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lw s2, 2016(sp)
 ; RV32I-WITHFP-NEXT:    lw s1, 2020(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 2024(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 2028(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
 ; RV32I-WITHFP-NEXT:    ret
   %data = alloca [ 100000 x i32 ] , align 4

llvm/test/CodeGen/RISCV/split-offsets.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 
 ; Check that memory accesses to array elements with large offsets have those
 ; offsets split into a base offset, plus a smaller offset that is folded into
 ; the memory operation. We should also only compute that base offset once,
 ; since it can be shared for all memory operations in this test.
 define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
 ; RV32I-LABEL: test1:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    lui a2, 20
-; RV32I-NEXT:    addi a2, a2, -1920
+; RV32I-NEXT:    addi a2, zero, 625
+; RV32I-NEXT:    slli a2, a2, 7
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    sw a2, 0(a0)
 ; RV32I-NEXT:    addi a3, zero, 1
 ; RV32I-NEXT:    sw a3, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a1)
 ; RV32I-NEXT:    sw a2, 4(a1)

 }
 
 ; Ditto. Check it when the GEPs are not in the entry block.
 define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
 ; RV32I-LABEL: test2:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    lw a4, 0(a0)
-; RV32I-NEXT:    lui a0, 20
-; RV32I-NEXT:    addi a5, a0, -1920
+; RV32I-NEXT:    addi a0, zero, 625
+; RV32I-NEXT:    slli a5, a0, 7
 ; RV32I-NEXT:    add a0, a1, a5
 ; RV32I-NEXT:    add a1, a4, a5
 ; RV32I-NEXT:    bge a3, a2, .LBB1_2
 ; RV32I-NEXT:  .LBB1_1: # %while_body
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    addi a4, a3, 1
 ; RV32I-NEXT:    sw a4, 0(a1)
 ; RV32I-NEXT:    sw a3, 4(a1)

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lh a2, 0(a1)
 ; RV32I-NEXT:    lh a0, 12(a1)
 ; RV32I-NEXT:    lh a3, 8(a1)
 ; RV32I-NEXT:    lh a1, 4(a1)
 ; RV32I-NEXT:    srli a4, a2, 26
 ; RV32I-NEXT:    add a4, a2, a4
-; RV32I-NEXT:    lui a6, 16
-; RV32I-NEXT:    addi a5, a6, -64
+; RV32I-NEXT:    addi a5, zero, 1023
+; RV32I-NEXT:    slli a5, a5, 6
 ; RV32I-NEXT:    and a4, a4, a5
 ; RV32I-NEXT:    sub s2, a2, a4
 ; RV32I-NEXT:    srli a2, a1, 27
 ; RV32I-NEXT:    add a2, a1, a2
-; RV32I-NEXT:    addi a4, a6, -32
-; RV32I-NEXT:    and a2, a2, a4
+; RV32I-NEXT:    lui a4, 16
+; RV32I-NEXT:    addi a5, a4, -32
+; RV32I-NEXT:    and a2, a2, a5
 ; RV32I-NEXT:    sub s3, a1, a2
 ; RV32I-NEXT:    srli a1, a3, 29
 ; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    addi a2, a6, -8
+; RV32I-NEXT:    addi a2, a4, -8
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub s1, a3, a1
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    sh a0, 6(s0)
 ; RV32I-NEXT:    sh s1, 4(s0)
 ; RV32I-NEXT:    sh s3, 2(s0)
 ; RV32I-NEXT:    sh s2, 0(s0)

 ; RV32IM-NEXT:    srli a2, a5, 31
 ; RV32IM-NEXT:    srli a5, a5, 6
 ; RV32IM-NEXT:    add a2, a5, a2
 ; RV32IM-NEXT:    addi a5, zero, 95
 ; RV32IM-NEXT:    mul a2, a2, a5
 ; RV32IM-NEXT:    sub a7, a4, a2
 ; RV32IM-NEXT:    srli a4, a1, 26
 ; RV32IM-NEXT:    add a4, a1, a4
+; RV32IM-NEXT:    addi a5, zero, 1023
+; RV32IM-NEXT:    slli a5, a5, 6
+; RV32IM-NEXT:    and a4, a4, a5
+; RV32IM-NEXT:    sub a1, a1, a4
+; RV32IM-NEXT:    srli a4, a3, 27
+; RV32IM-NEXT:    add a4, a3, a4
 ; RV32IM-NEXT:    lui a5, 16
-; RV32IM-NEXT:    addi a2, a5, -64
+; RV32IM-NEXT:    addi a2, a5, -32
 ; RV32IM-NEXT:    and a2, a4, a2
-; RV32IM-NEXT:    sub a1, a1, a2
-; RV32IM-NEXT:    srli a2, a3, 27
-; RV32IM-NEXT:    add a2, a3, a2
-; RV32IM-NEXT:    addi a4, a5, -32
-; RV32IM-NEXT:    and a2, a2, a4
 ; RV32IM-NEXT:    sub a2, a3, a2
 ; RV32IM-NEXT:    srli a3, a6, 29
 ; RV32IM-NEXT:    add a3, a6, a3
 ; RV32IM-NEXT:    addi a4, a5, -8
 ; RV32IM-NEXT:    and a3, a3, a4
 ; RV32IM-NEXT:    sub a3, a6, a3
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)

 ; RV32I-NEXT:    addi a1, zero, 654
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    addi a1, zero, 23
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
 ; RV32I-NEXT:    sh a0, 6(s0)
 ; RV32I-NEXT:    sh s1, 4(s0)
 ; RV32I-NEXT:    sh s3, 2(s0)
 ; RV32I-NEXT:    lw s3, 12(sp)
 ; RV32I-NEXT:    lw s2, 16(sp)

 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a1, a1, a4
 ; RV32IM-NEXT:    lui a4, 395996
 ; RV32IM-NEXT:    addi a4, a4, -2009
 ; RV32IM-NEXT:    mulh a4, a2, a4
 ; RV32IM-NEXT:    srli a5, a4, 31
 ; RV32IM-NEXT:    srli a4, a4, 11
 ; RV32IM-NEXT:    add a4, a4, a5
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a2, a2, a4
 ; RV32IM-NEXT:    sh zero, 0(a0)
 ; RV32IM-NEXT:    sh a2, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a3, 2(a0)
 ; RV32IM-NEXT:    ret
 ;

 ; RV32I-NEXT:    srli a1, a2, 17
 ; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    lui a3, 8
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    sub s3, a2, a1
 ; RV32I-NEXT:    addi a1, zero, 23
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
 ; RV32I-NEXT:    sh a0, 6(s0)
 ; RV32I-NEXT:    sh s1, 4(s0)
 ; RV32I-NEXT:    sh s3, 2(s0)
 ; RV32I-NEXT:    lw s3, 12(sp)
 ; RV32I-NEXT:    lw s2, 16(sp)

 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a3, a3, a4
 ; RV32IM-NEXT:    lui a4, 395996
 ; RV32IM-NEXT:    addi a4, a4, -2009
 ; RV32IM-NEXT:    mulh a4, a1, a4
 ; RV32IM-NEXT:    srli a5, a4, 31
 ; RV32IM-NEXT:    srli a4, a4, 11
 ; RV32IM-NEXT:    add a4, a4, a5
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a1, a1, a4
 ; RV32IM-NEXT:    srli a4, a2, 17
 ; RV32IM-NEXT:    add a4, a2, a4
 ; RV32IM-NEXT:    lui a5, 8
 ; RV32IM-NEXT:    and a4, a4, a5
 ; RV32IM-NEXT:    sub a2, a2, a4
 ; RV32IM-NEXT:    sh zero, 0(a0)

 ; RV32I-NEXT:    mv s9, a1
 ; RV32I-NEXT:    addi a2, zero, 23
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s5
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __moddi3
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a2, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a2, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __moddi3
 ; RV32I-NEXT:    sw a1, 28(s0)
 ; RV32I-NEXT:    sw a0, 24(s0)
 ; RV32I-NEXT:    sw s1, 20(s0)
 ; RV32I-NEXT:    sw s4, 16(s0)

 ; RV32IM-NEXT:    mv s9, a1
 ; RV32IM-NEXT:    addi a2, zero, 23
 ; RV32IM-NEXT:    mv a0, s4
 ; RV32IM-NEXT:    mv a1, s5
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __moddi3
 ; RV32IM-NEXT:    mv s4, a0
 ; RV32IM-NEXT:    mv s1, a1
-; RV32IM-NEXT:    lui a0, 1
-; RV32IM-NEXT:    addi a2, a0, 1327
+; RV32IM-NEXT:    lui a0, 694144
+; RV32IM-NEXT:    srli a2, a0, 19
 ; RV32IM-NEXT:    mv a0, s2
 ; RV32IM-NEXT:    mv a1, s3
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __moddi3
 ; RV32IM-NEXT:    sw a1, 28(s0)
 ; RV32IM-NEXT:    sw a0, 24(s0)
 ; RV32IM-NEXT:    sw s1, 20(s0)
 ; RV32IM-NEXT:    sw s4, 16(s0)

llvm/test/CodeGen/RISCV/stack-realignment.ll

 ; RV32I-LABEL: caller1024:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
 ; RV32I-NEXT:    addi sp, sp, -1040
 ; RV32I-NEXT:    andi sp, sp, -1024
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    addi a0, zero, 1
+; RV32I-NEXT:    slli a0, a0, 11
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    addi a0, zero, 3
+; RV32I-NEXT:    slli a0, a0, 10
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    addi sp, sp, 1040
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller1024:

 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, 16
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    addi a0, zero, 3
+; RV32I-NEXT:    slli a0, a0, 11
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, 16
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret

 
 define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    addi a0, a0, -2032
+; RV32I-NEXT:    addi a0, zero, 641
+; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
 ; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    addi a0, a0, -2032
+; RV32I-NEXT:    addi a0, zero, 641
+; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

 ; RV32I-NEXT:    addi a1, zero, 654
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    addi a1, zero, 23
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
 ; RV32I-NEXT:    sh a0, 6(s0)
 ; RV32I-NEXT:    sh s1, 4(s0)
 ; RV32I-NEXT:    sh s3, 2(s0)
 ; RV32I-NEXT:    lw s3, 12(sp)
 ; RV32I-NEXT:    lw s2, 16(sp)

 ; RV32IM-NEXT:    srli a4, a4, 4
 ; RV32IM-NEXT:    addi a5, zero, 23
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a1, a1, a4
 ; RV32IM-NEXT:    lui a4, 395996
 ; RV32IM-NEXT:    addi a4, a4, -2009
 ; RV32IM-NEXT:    mulhu a4, a3, a4
 ; RV32IM-NEXT:    srli a4, a4, 11
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a3, a3, a4
 ; RV32IM-NEXT:    sh zero, 0(a0)
 ; RV32IM-NEXT:    sh a3, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)
 ; RV32IM-NEXT:    ret
 ;

 ; RV32I-NEXT:    mv s9, a1
 ; RV32I-NEXT:    addi a2, zero, 23
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s5
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __umoddi3
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a2, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a2, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __umoddi3
 ; RV32I-NEXT:    sw a1, 28(s0)
 ; RV32I-NEXT:    sw a0, 24(s0)
 ; RV32I-NEXT:    sw s1, 20(s0)
 ; RV32I-NEXT:    sw s4, 16(s0)

 ; RV32IM-NEXT:    mv s9, a1
 ; RV32IM-NEXT:    addi a2, zero, 23
 ; RV32IM-NEXT:    mv a0, s4
 ; RV32IM-NEXT:    mv a1, s5
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __umoddi3
 ; RV32IM-NEXT:    mv s4, a0
 ; RV32IM-NEXT:    mv s1, a1
-; RV32IM-NEXT:    lui a0, 1
-; RV32IM-NEXT:    addi a2, a0, 1327
+; RV32IM-NEXT:    lui a0, 694144
+; RV32IM-NEXT:    srli a2, a0, 19
 ; RV32IM-NEXT:    mv a0, s2
 ; RV32IM-NEXT:    mv a1, s3
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __umoddi3
 ; RV32IM-NEXT:    sw a1, 28(s0)
 ; RV32IM-NEXT:    sw a0, 24(s0)
 ; RV32IM-NEXT:    sw s1, 20(s0)
 ; RV32IM-NEXT:    sw s4, 16(s0)

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

 
 define i32 @test_zext_i16() nounwind {
 ; RV32I-LABEL: test_zext_i16:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(shorts)
 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -120
+; RV32I-NEXT:    lui a2, 1046656
+; RV32I-NEXT:    srli a2, a2, 16
 ; RV32I-NEXT:    xor a1, a1, a2
 ; RV32I-NEXT:    xori a0, a0, 7
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    bnez a0, .LBB1_2
 ; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_2: # %if.then

llvm/test/MC/RISCV/rv32c-aliases-valid.s

 # CHECK-EXPAND: c.li a0, 1
 li x10, 1
 # CHECK-EXPAND: c.li a0, -1
 li x10, -1
 # CHECK-EXPAND: addi a0, zero, 2047
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-EXPAND: c.li a1, 1
+# CHECK-EXPAND: c.slli a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2047
+# CHECK-EXPAND: lui a1, 524544
+# CHECK-EXPAND: c.srli a1, 20
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 2047
 li x11, -2049
 # CHECK-EXPAND: c.lui a1, 1
 # CHECK-EXPAND: c.addi a1, -1
 li x11, 4095
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: c.addi a1, 1
 li x11, -4095
 # CHECK-EXPAND: c.lui a2, 1
 li x12, 4096
 # CHECK-EXPAND: lui a2, 1048575
 li x12, -4096
 # CHECK-EXPAND: c.lui a2, 1
 # CHECK-EXPAND: c.addi a2, 1
 li x12, 4097
 # CHECK-EXPAND: lui a2, 1048575
 # CHECK-EXPAND: c.addi a2, -1
 li x12, -4097
-# CHECK-EXPAND: lui a2, 524288
-# CHECK-EXPAND: c.addi a2, -1
+# CHECK-EXPAND: c.li a2, -1
+# CHECK-EXPAND: c.srli a2, 1
 li x12, 2147483647
 # CHECK-EXPAND: lui a2, 524288
 # CHECK-EXPAND: c.addi a2, 1
 li x12, -2147483647
 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000
 
 # CHECK-EXPAND: lui a2, 524288
 li x12, 0x80000000
 # CHECK-EXPAND: c.li a2, -1
 li x12, 0xFFFFFFFF
 
 # CHECK-EXPAND: c.mv sp, sp
 addi x2, x2, 0

llvm/test/MC/RISCV/rv32i-aliases-valid.s

 # CHECK-EXPAND: addi a0, zero, 1
 li x10, 1
 # CHECK-EXPAND: addi a0, zero, -1
 li x10, -1
 # CHECK-EXPAND: addi a0, zero, 2047
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-EXPAND: addi a1, zero, 1
+# CHECK-EXPAND: slli a1, a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2047
+# CHECK-EXPAND: lui a1, 524544
+# CHECK-EXPAND: srli a1, a1, 20
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 2047
 li x11, -2049
 # CHECK-EXPAND: lui a1, 1
 # CHECK-EXPAND: addi a1, a1, -1
 li x11, 4095
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 1
 li x11, -4095
 # CHECK-EXPAND: lui a2, 1
 li x12, 4096
 # CHECK-EXPAND: lui a2, 1048575
 li x12, -4096
 # CHECK-EXPAND: lui a2, 1
 # CHECK-EXPAND: addi a2, a2, 1
 li x12, 4097
 # CHECK-EXPAND: lui a2, 1048575
 # CHECK-EXPAND: addi a2, a2, -1
 li x12, -4097
-# CHECK-EXPAND: lui a2, 524288
-# CHECK-EXPAND: addi a2, a2, -1
+# CHECK-EXPAND: addi a2, zero, -1
+# CHECK-EXPAND: srli a2, a2, 1
 li x12, 2147483647
 # CHECK-EXPAND: lui a2, 524288
 # CHECK-EXPAND: addi a2, a2, 1
 li x12, -2147483647
 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000

 # CHECK-OBJ-NOALIAS: addi a0, zero, 0
 # CHECK-OBJ: R_RISCV_LO12
 li a0, %lo(foo)
 # CHECK-OBJ-NOALIAS: addi a0, zero, 0
 # CHECK-OBJ: R_RISCV_PCREL_LO12
 li a0, %pcrel_lo(.Lpcrel_hi0)
 
 .equ CONST, 0x123456
-# CHECK-EXPAND: lui a0, 291
-# CHECK-EXPAND: addi a0, a0, 1110
+# CHECK-EXPAND: lui a0, 596523
+# CHECK-EXPAND: srli a0, a0, 11
 li a0, CONST
 # CHECK-EXPAND: lui a0, 291
 # CHECK-EXPAND: addi a0, a0, 1111
 li a0, CONST+1
 
 .equ CONST, 0x654321
 # CHECK-EXPAND: lui a0, 1620
 # CHECK-EXPAND: addi a0, a0, 801