[PowerPC] Add linker opt for PC Relative GOT indirect accesses

[stefanp]

Summary

A linker optimization is available on PowerPC for GOT indirect PCRelative loads.

The idea is that we can mark a usual GOT indirect load:

pld 3, vec@got@pcrel(0), 1
lwa 3, 4(3)

With a relocation to say that if we don't need to go through the GOT we can let the linker further optimize this and replace a load with a nop.

  pld 3, vec@got@pcrel(0), 1
.Lpcrel1:
.reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
  lwa 3, 4(3)

Which will eventually turn it into this by the linker (if we don't actually need to go through the GOT):

plwa 3, vec@got@pcrel+4(0), 1
nop

To create those relocations on the compiler side this patch adds an MCSymbol operand on the pld and the subsequent load or store that depends on it.
This symbol is then read in the MC layer and is used to match the two instructions together.

[NeHuang]

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

108

We can merge it with the check above (97-103) since it also checks for isUsingPCRelativeCalls()

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

415 ↗

(On Diff #263713)

nit: static uint64_t UseCounter = 0;

llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

7

Do we need to add a test description here?

[stefanp]

Address review comments.

[efriedma]

Which will eventually turn it into this by the linker (if we don't actually need to go through the GOT):

plwa 3, vec@got@pcrel+4(0), 1
nop

Which instruction gets replaced by a nop, the pld or the lwa?

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

401 ↗

(On Diff #265998)

I think the hasPCRelativeForm check subsumes a bunch of the other checks: for example, if an instruction has one of the listed opcodes, it can't be a call.

[amyk]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

95

Maybe add a short comment here about the relocation printing, since other cases are also documented.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

504 ↗

(On Diff #265998)

nit: space after the :.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

405 ↗

(On Diff #265998)

Would it be good to check if it is indeed a store instruction? Something like Use.mayStore(), though I realize it might be a bit redundant if we reached this part of the code.

[stefanp]

In D79864#2058355, @efriedma wrote:

Which will eventually turn it into this by the linker (if we don't actually need to go through the GOT):

plwa 3, vec@got@pcrel+4(0), 1
nop

Which instruction gets replaced by a nop, the pld or the lwa?

The pld is replaced by the plwa and the lwa is replaced by the nop.

[efriedma]

Then your code is missing some checks: you're assuming the operand and the result of the load will be allocated in the same register, without actually verifying that anywhere.

[efriedma]

Just looked at what I wrote, and the issue I'm looking for isn't clear.

The code doesn't require that requiring that the pld and the lwa

[efriedma]

And now I somehow submitted before I was done writing my comment. Trying again.

---

Just looked at what I wrote, and the issue I'm seeing isn't clear.

The code doesn't require that the pld and the lwa are adjacent. Therefore, it's possible that some instruction between the pld and the lwa writes to the destination register of the lwa. If there is such an instruction, the linker optimization would cause a miscompile: the loaded value would be clobbered.

[stefanp]

In D79864#2061105, @efriedma wrote:

Just looked at what I wrote, and the issue I'm seeing isn't clear.

The code doesn't require that the pld and the lwa are adjacent. Therefore, it's possible that some instruction between the pld and the lwa writes to the destination register of the lwa. If there is such an instruction, the linker optimization would cause a miscompile: the loaded value would be clobbered.

You are correct I have not checked for that. I will have to think about how to resolve the issue because I add the linker opt flag to the instruction before register allocation so I can't just check that the registers are the same at that time.
In the meantime, I will fixup the feedback from the other comments.

I could re-verify the instruction after register allocation in another peephole perhaps...

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

401 ↗

(On Diff #265998)

You are correct, the previous checks are redundant. I'll remove all four of the previous checks.

405 ↗

(On Diff #265998)

That's a good question. I don't think we need to check if this is a store because:

1. The check hasPCRelativeForm limits the valid instructions for this.

AND

2. If this is a load from the valid instruction pool then operand zero is not a use (And we know that Use is a use.)

[stefanp]

Addressed some of the review comments.
Added code that I had meant to have in this patch but forgot.

Still need to address the concern where the output for the second load is clobbered between the two loads.

[stefanp]

Moved the linker opt detection into the pre-emit peephole.
This should solve the problem where instructions between the PLD and the second load/store make the optimization unsafe.

[hubert.reinterpretcast]

Can the subject line of the revision characterize the addition as something more specific than a "new linker optimization"?

[anil9]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

148

nit : Obtian -> Obtaini

166

Can this -8 be handled in some other way, like defined above as something. Looks a bit like a magic number.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

49

Indent ?

222

nit:

We can get one operand, check condition and exit, instead of getting both of them and then checkiing one by one.

237

This did not fit in one line ?

256

" if this is valid to mark it as a "

llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

7

enabled, it is

[amyk]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

137

Could you rephrase this sentence? Not sure if it's just me but it seems a little confusing to read.

149

s/instrctions/instructions

156

s/instrctions/instructions

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

251

Could we do something like

if (!UseFound.isValid())
  continue;

maybe?

[stefanp]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

148

I'm not sure what you want here... Did I have typo it before and have Obaini there?

166

The 8 is the size of a prefixed instruction in bytes. I don't want to define it somewhere because it is used only in a couple of places but I will add a comment to explain it. This whole section deserves a better comment.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

237

no... off by one character. :(

[stefanp]

Address Review Comments.

[stefanp]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

148

Of course I typoed the comment. :(
Anyway, I think Obtain is fine.

[stefanp]

@efriedma
Would you mind looking at the new implementation of this patch to see if you can spot any issues.
Any feed back is very much appreciated!

[efriedma]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

129

The way this is structured is a little confusing. If the instruction is a pld, it returns the label; if it's some other instruction, it emits a relocation itself. It would probably be more clear to split the "emit a relocation" part into a separate function.

154

Isn't getContext().getOrCreateSymbol(SymExpr->getSymbol().getName()); equivalent to SymExpr->getSymbol()?

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

264

To be on the safe side, I think I'd add an implicit def of the register to the pld, and an implicit use to the load, so it's clear to any later passes that the register is actually live between the pld and the load

271

Storing a counter in a static variable isn't threadsafe or deterministic. Please store the counter in PPCFunctionInfo or something like that.

Or actually, in this context, you could probably use createTempSymbol, which manages the counter for you.

[stefanp]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

154

Unfortunately it is not the same thing.
In the case of SymExpr->getSymbol() we get a const MCSymbol& while in the case of getContext().getOrCreateSymbol(SymExpr->getSymbol().getName()); we get an MCSymbol*. The problem is that I call emitLabel and that requires a MCSymbol*. The const doesn't let me call that function and I don't want to const cast or something like that.

There may, however, still be a better way to do this. I just don't know what that is.

[stefanp]

Addressed review comments.

[nemanjai]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

94

I think it would be clear if at the top level here we have something like this:

// If the instruction is a part of the GOT to PC-Rel link time optimization
// instruction pair, return a value, otherwise return None. A true returned
// value means the instruction is the PLDpc and a false value means it is
// the user instruction.
Optional<bool> IsPartOfGOTToPCRelPair = isPartOfGOTToPCRelPair(Inst, STI);

// User of the GOT-indirect address.
if (IsPartOfGOTToPCRelPair.hasValue() && !IsPartOfGOTToPCRelPair.getValue())
  emitGOTToPCRelReloc(Inst);

// existing code to emit the instruction

// Producer of the GOT-indirect address.
if (IsPartOfGOTToPCRelPair.hasValue() && IsPartOfGOTToPCRelPair.getValue())
  emitGOTToPCRelLabel(Inst);

128

This needs to have both a more descriptive name and a comment describing what it does. A few requests here:

1. Functions whose names indicate they are queries (i.e. check... etc.) should probably not modify code. Either check something or modify something.
2. Avoid the very generic phrase "linker opt{imization}" throughout this code. You should pick a name for this optimization and use it throughout. Perhaps a name such as "GOT to PC-Rel relaxation" or "Link time GOT to PC-Rel optimization".
3. One or two examples of the kind of MCInst for which this will return a non-null symbol.

168

// The reason we place the label after the PLDpc instruction is that there
// may be an alignment nop before it since prefixed instructions must not
// cross a 64-byte boundary (please see
// PPCELFStreamer::emitPrefixedInstruction()). When referring to the
// label, we subtract the width of a prefixed instruction (8 bytes) to ensure
// we refer to the PLDpc.

181

TmpLabel is just the current location, right? Please name it as such if so.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

99

Could we maybe pull out isPartOfGOTToPCRelPair() I mentioned above and use it here as well as in the streamer code?

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

215

The algorithm here is a bit hard to follow by just reading the code. We search forward looking for a PLDpc. When we find one, we search forward for a user. Once we find the user, if the user defines any registers, we search back to make sure there are no intervening uses or defs of that register.

It might be easier to follow if we do a single pass to collect all address defs and uses and then check code in between for any candidate pairs.
Something along these lines:

struct GOTDefUsePair {
  MachineBasicBlock::iterator DefInst;
  MachineBasicBlock::iterator UseInst;
  Register DefReg;
  Register UseInstDef;
};

SmallVector<GOTDefUsePair> Pairs;
loop over the block
  if (instruction is a candidate PLDpc)
    create a pair object and push it to Pairs
    continue
  if (instruction is a use of any defs in Pairs)
    if (not a kill)
      remove pair object from Pairs (this can also be done by keeping a Valid flag for each pair)
      continue
    add the use iterator and register (if any) to the pair in question

Then after collecting instruction pairs, loop over the vector to eliminate invalid pairs (due to register uses/defs, etc.) and finally add the symbols.

[stefanp]

Address review comments.
Mainly reworked two functions: isPartOfGOTToPCRelPair and addLinkerOpt.
Unfortunately I was not able to move isPartOfGOTToPCRelPair out of PPCELFStreamer because I was not able to find a good place for it.

[stefanp]

Gentle ping

[nemanjai]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

99

// For example, the load that will get the relocation as follows:
// .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
//  lwa 3, 4(3)

113

// For example, the prefixed load from the got that will get the label as follows:
//  pld 3, vec@got@pcrel(0), 1
// .Lpcrel1:

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

110

Is there not something like printLabel() and printRelocDirective() for this? It seems odd to be manually printing it like this.
If there isn't that's fine, just seems odd.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

246

I know this is based on my suggestion, but I think the name doesn't make sense if this is a store (since a store does not define anything). Perhaps just UseReg is fine.

255

I think a simpler implementation for lines 255-311 would be something like this:

for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
  // Look for the initial GOT indirect load.
  if (isGOTPLDpc(*BBI)) {
    GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(),
                              BBI->getOperand(0).getReg(), PPC::NoRegister,
                              true};
    CandPairs.push_back(CurrentPair);
    continue;
  }

  // We haven't encountered any new PLD instructions, nothing to check.
  if (CandPairs.empty())
    continue;

  // Run through the candidate pairs and see if any of the registers
  // defined in the PLD instructions are used by this instruction.
  // Note: the size of CandPairs can change in the loop.
  for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) {
    GOTDefUsePair &Pair = CandPairs[Idx];
    // The instruction does not use or modify this PLD's def reg, ignore it.
    if (!BBI->readsRegister(Pair.DefReg, TRI) &&
        !BBI->modifiesRegister(Pair.DefReg, TRI))
      continue;

    // The use needs to be used in the address compuation and not
    // as the register being stored for a store.
    const MachineOperand *UseOp =
        hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr;

    // Check for a valid use.
    if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
        UseOp->isUse() && UseOp->isKill()) {
      Pair.UseInst = BBI;
      Pair.UseInstDef = BBI->getOperand(0).getReg();
      ValidPairs.push_back(Pair);
    }
    CandPairs.erase(CandPairs.begin() + Idx);
  }
}

// Go through all of the pairs and check for any more valid uses.
for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) {
  // We shouldn't be here if we don't have a valid pair.
  assert(Pair->UseInst.isValid() && Pair->StillValid &&
         "Kept an invalid def/use pair for GOT PCRel opt");

The idea is that after the loop over the basic block, we just have a data structure containing pairs of (PLD, MemAccess) where the register defined by PLD is guaranteed to not have uses in between them. Then for each such pair, we check for defs/uses of the register defined by the MemAccess and we're done.

268

s/futher/further

llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

160

; FIXME: we should always convert X-Form instructions that use
; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.

391

Please add attributes #0 = { nounwind } and decorate the functions with it so we don't get the .cfi directives since they just make the test case more busy.

[stefanp]

Changed the way that the peephole finds candidates according to the suggestion by Nemanja.
Added/fixed some comments.
Cleaned up the testcase.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

110

Yes it is a bit funny.
There is a standard way to print the label:

SymExpr->print(O, &MAI);

The problem is that if I do it that I way I get this:

.Lpcrel3@<<invalid>>

I have the MCSymbolRefExpr::VK_PPC_PCREL_OPT there because I need it internally but I don't want it printed.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

215

This makes sense to me. I'll use this code.

[efriedma]

Current approach seems fine.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

110

There's a method MCSymbol::print

[stefanp]

Modified static_cast to cast.
Made use of MCSymbol::print.

[stefanp]

I should not have changed the cast.
Changed it back now.

[nemanjai]

The remaining comments are minor nits that can be addressed on commit. LGTM.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

315

I think you can just flip this to

if (!Pair->StillValid)
  continue;

and reduce the nesting in the following code.

317

Elaborate slightly. Implicit def of what and implicit use of what and why.

329

I think the name LabelNum is a bit awkward. Maybe it should be something like PCRelLabel or PCRelNumberedLabel?

llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

46

Why is there no relocation that refers to the store? Similarly below.

106

Please add a FIXME here for us to follow up on this. We should favour the D-Forms in cases such as this so that they can be optimized.

[stefanp]

Flipped the if statement.
Fixed a comment in the source and added a couple more comments in the test case.

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
     VK_PPC_TLSLD,           // symbol@tlsld
     VK_PPC_LOCAL,           // symbol@local
     VK_PPC_NOTOC,           // symbol@notoc
+    VK_PPC_PCREL_OPT,       // .reloc expr, R_PPC64_PCREL_OPT, expr
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
 
     VK_Hexagon_LO16,
     VK_Hexagon_HI16,
     VK_Hexagon_GPREL,
     VK_Hexagon_GD_GOT,
     VK_Hexagon_LD_GOT,

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
   case VK_PPC_TLSLD: return "tlsld";
   case VK_PPC_LOCAL: return "local";
   case VK_PPC_NOTOC: return "notoc";
+  case VK_PPC_PCREL_OPT: return "<<invalid>>";
   case VK_COFF_IMGREL32: return "IMGREL";
   case VK_Hexagon_LO16: return "LO16";
   case VK_Hexagon_HI16: return "HI16";
   case VK_Hexagon_GPREL: return "GPREL";
   case VK_Hexagon_GD_GOT: return "GDGOT";
   case VK_Hexagon_LD_GOT: return "LDGOT";
   case VK_Hexagon_GD_PLT: return "GDPLT";
   case VK_Hexagon_LD_PLT: return "LDPLT";

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h

PPCELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> MAB,
                  std::unique_ptr<MCCodeEmitter> Emitter);
 
   void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
 
   // EmitLabel updates LastLabel and LastLabelLoc when a new label is emitted.
   void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override;
 private:
   void emitPrefixedInstruction(const MCInst &Inst, const MCSubtargetInfo &STI);
+  void emitGOTToPCRelReloc(const MCInst &Inst);
+  void emitGOTToPCRelLabel(const MCInst &Inst);
 };
 
+// Check if the instruction Inst is part of a pair of instructions that make up
+// a link time GOT PC Rel optimization.
+Optional<bool> isPartOfGOTToPCRelPair(const MCInst &Inst,
+                                      const MCSubtargetInfo &STI);
+
 MCELFStreamer *createPPCELFStreamer(MCContext &Context,
                                     std::unique_ptr<MCAsmBackend> MAB,
                                     std::unique_ptr<MCObjectWriter> OW,
                                     std::unique_ptr<MCCodeEmitter> Emitter);
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_PPC_MCELFSTREAMER_PPCELFSTREAMER_H

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

 // because 8 byte instructions are not allowed to cross 64 byte boundaries
 // and by aliging anything that is within 4 bytes of the boundary we can
 // guarantee that the 8 byte instructions do not cross that boundary.
 //
 //===----------------------------------------------------------------------===//
 
 
 #include "PPCELFStreamer.h"
+#include "PPCFixupKinds.h"
 #include "PPCInstrInfo.h"
 #include "PPCMCCodeEmitter.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInst.h"
void PPCELFStreamer::emitPrefixedInstruction(const MCInst &Inst,
   }
 }
 
 void PPCELFStreamer::emitInstruction(const MCInst &Inst,
                                      const MCSubtargetInfo &STI) {
   PPCMCCodeEmitter *Emitter =
       static_cast<PPCMCCodeEmitter*>(getAssembler().getEmitterPtr());
 
+  // If the instruction is a part of the GOT to PC-Rel link time optimization
+  // instruction pair, return a value, otherwise return None. A true returned
+  // value means the instruction is the PLDpc and a false value means it is
+  // the user instruction.
+  Optional<bool> IsPartOfGOTToPCRelPair = isPartOfGOTToPCRelPair(Inst, STI);
+
+  // User of the GOT-indirect address.
+  // For example, the load that will get the relocation as follows:
+  // .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+  //  lwa 3, 4(3)
+  if (IsPartOfGOTToPCRelPair.hasValue() && !IsPartOfGOTToPCRelPair.getValue())
+    emitGOTToPCRelReloc(Inst);
+
   // Special handling is only for prefixed instructions.
   if (!Emitter->isPrefixedInstruction(Inst)) {
     MCELFStreamer::emitInstruction(Inst, STI);
     return;
   }
   emitPrefixedInstruction(Inst, STI);
+
+  // Producer of the GOT-indirect address.
+  // For example, the prefixed load from the got that will get the label as
+  // follows:
+  //  pld 3, vec@got@pcrel(0), 1
+  // .Lpcrel1:
+  if (IsPartOfGOTToPCRelPair.hasValue() && IsPartOfGOTToPCRelPair.getValue())
+    emitGOTToPCRelLabel(Inst);
 }
 
 void PPCELFStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) {
   LastLabel = Symbol;
   LastLabelLoc = Loc;
   MCELFStreamer::emitLabel(Symbol);
 }
 
+// This linker time GOT PC Relative optimization relocation will look like this:
+//   pld <reg> symbol@got@pcrel
+// <Label###>:
+//   .reloc Label###-8,R_PPC64_PCREL_OPT,.-(Label###-8)
+//   load <loadedreg>, 0(<reg>)
+// The reason we place the label after the PLDpc instruction is that there
+// may be an alignment nop before it since prefixed instructions must not
+// cross a 64-byte boundary (please see
+// PPCELFStreamer::emitPrefixedInstruction()). When referring to the
+// label, we subtract the width of a prefixed instruction (8 bytes) to ensure
+// we refer to the PLDpc.
+void PPCELFStreamer::emitGOTToPCRelReloc(const MCInst &Inst) {
+  // Get the last operand which contains the symbol.
+  const MCOperand &Operand = Inst.getOperand(Inst.getNumOperands() - 1);
+  assert(Operand.isExpr() && "Expecting an MCExpr.");
+  // Cast the last operand to MCSymbolRefExpr to get the symbol.
+  const MCExpr *Expr = Operand.getExpr();
+  const MCSymbolRefExpr *SymExpr = static_cast<const MCSymbolRefExpr *>(Expr);
+  assert(SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT &&
+         "Expecting a symbol of type VK_PPC_PCREL_OPT");
+  MCSymbol *LabelSym =
+      getContext().getOrCreateSymbol(SymExpr->getSymbol().getName());
+  const MCExpr *LabelExpr = MCSymbolRefExpr::create(LabelSym, getContext());
+  const MCExpr *Eight = MCConstantExpr::create(8, getContext());
+  // SubExpr is just Label###-8
+  const MCExpr *SubExpr =
+      MCBinaryExpr::createSub(LabelExpr, Eight, getContext());
+  MCSymbol *CurrentLocation = getContext().createTempSymbol();
+  const MCExpr *CurrentLocationExpr =
+      MCSymbolRefExpr::create(CurrentLocation, getContext());
+  // SubExpr2 is .-(Label###-8)
+  const MCExpr *SubExpr2 =
+      MCBinaryExpr::createSub(CurrentLocationExpr, SubExpr, getContext());
+
+  MCDataFragment *DF = static_cast<MCDataFragment *>(LabelSym->getFragment());
+  assert(DF && "Expecting a valid data fragment.");
+  MCFixupKind FixupKind = static_cast<MCFixupKind>(FirstLiteralRelocationKind +
+                                                   ELF::R_PPC64_PCREL_OPT);
+  DF->getFixups().push_back(
+      MCFixup::create(LabelSym->getOffset() - 8, SubExpr2,
+                      FixupKind, Inst.getLoc()));
+  emitLabel(CurrentLocation, Inst.getLoc());
+}
+
+// Emit the label that immediately follows the PLDpc for a link time GOT PC Rel
+// optimization.
+void PPCELFStreamer::emitGOTToPCRelLabel(const MCInst &Inst) {
+  // Get the last operand which contains the symbol.
+  const MCOperand &Operand = Inst.getOperand(Inst.getNumOperands() - 1);
+  assert(Operand.isExpr() && "Expecting an MCExpr.");
+  // Cast the last operand to MCSymbolRefExpr to get the symbol.
+  const MCExpr *Expr = Operand.getExpr();
+  const MCSymbolRefExpr *SymExpr = static_cast<const MCSymbolRefExpr *>(Expr);
+  assert(SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT &&
+         "Expecting a symbol of type VK_PPC_PCREL_OPT");
+  MCSymbol *LabelSym =
+      getContext().getOrCreateSymbol(SymExpr->getSymbol().getName());
+  emitLabel(LabelSym, Inst.getLoc());
+}
+
+// This funciton checks if the parameter Inst is part of the setup for a link
+// time GOT PC Relative optimization. For example in this situation:
+// <MCInst PLDpc <MCOperand Reg:282> <MCOperand Expr:(glob_double@got@pcrel)>
+//   <MCOperand Imm:0> <MCOperand Expr:(.Lpcrel@<<invalid>>)>>
+// <MCInst SOME_LOAD <MCOperand Reg:22> <MCOperand Imm:0> <MCOperand Reg:282>
+//   <MCOperand Expr:(.Lpcrel@<<invalid>>)>>
+// The above is a pair of such instructions and this function will not return
+// None for either one of them. In both cases we are looking for the last
+// operand <MCOperand Expr:(.Lpcrel@<<invalid>>)> which needs to be an MCExpr
+// and has the flag MCSymbolRefExpr::VK_PPC_PCREL_OPT. After that we just look
+// at the opcode and in the case of PLDpc we will return true. For the load
+// (or store) this function will return false indicating it has found the second
+// instruciton in the pair.
+Optional<bool> llvm::isPartOfGOTToPCRelPair(const MCInst &Inst,
+                                            const MCSubtargetInfo &STI) {
+  // Need at least two operands.
+  if (Inst.getNumOperands() < 2)
+    return None;
+
+  unsigned LastOp = Inst.getNumOperands() - 1;
+  // The last operand needs to be an MCExpr and it needs to have a variant kind
+  // of VK_PPC_PCREL_OPT. If it does not satisfy these conditions it is not a
+  // link time GOT PC Rel opt instruction and we can ignore it and return None.
+  const MCOperand &Operand = Inst.getOperand(LastOp);
+  if (!Operand.isExpr())
+    return None;
+
+  // Check for the variant kind VK_PPC_PCREL_OPT in this expression.
+  const MCExpr *Expr = Operand.getExpr();
+  const MCSymbolRefExpr *SymExpr = static_cast<const MCSymbolRefExpr *>(Expr);
+  if (!SymExpr || SymExpr->getKind() != MCSymbolRefExpr::VK_PPC_PCREL_OPT)
+    return None;
+
+  return (Inst.getOpcode() == PPC::PLDpc);
+}
+
 MCELFStreamer *llvm::createPPCELFStreamer(
     MCContext &Context, std::unique_ptr<MCAsmBackend> MAB,
     std::unique_ptr<MCObjectWriter> OW,
     std::unique_ptr<MCCodeEmitter> Emitter) {
   return new PPCELFStreamer(Context, std::move(MAB), std::move(OW),
                             std::move(Emitter));
 }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

if (TT.isOSAIX() &&
     O << ", ";
     printOperand(MI, 2, O);
     O << "(";
     printOperand(MI, 1, O);
     O << ")";
     return;
   }
 
+  // Check if the last operand is an expression with the variant kind
+  // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
+  // relocation and the .reloc directive needs to be added.
+  unsigned LastOp = MI->getNumOperands() - 1;
+  if (MI->getNumOperands() > 1) {
+    const MCOperand &Operand = MI->getOperand(LastOp);
+    if (Operand.isExpr()) {
+      const MCExpr *Expr = Operand.getExpr();
+      const MCSymbolRefExpr *SymExpr =
+          static_cast<const MCSymbolRefExpr *>(Expr);
+
+      if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
+        const MCSymbol &Symbol = SymExpr->getSymbol();
+        if (MI->getOpcode() == PPC::PLDpc) {
+          printInstruction(MI, Address, O);
+          O << "\n";
+          Symbol.print(O, &MAI);
+          O << ":";
+          return;
+        } else {
+          O << "\t.reloc ";
+          Symbol.print(O, &MAI);
+          O << "-8,R_PPC64_PCREL_OPT,.-(";
+          Symbol.print(O, &MAI);
+          O << "-8)\n";
+        }
+      }
+    }
+  }
+
   // Check for slwi/srwi mnemonics.
   if (MI->getOpcode() == PPC::RLWINM) {
     unsigned char SH = MI->getOperand(2).getImm();
     unsigned char MB = MI->getOperand(3).getImm();
     unsigned char ME = MI->getOperand(4).getImm();
     bool useSubstituteMnemonic = false;
     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
       O << "\tslwi "; useSubstituteMnemonic = true;

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// the current instruction address(pc), e.g., var@pcrel. Fixup is VK_PCREL.
     MO_PCREL_FLAG = 4,
 
     /// MO_GOT_FLAG - If this bit is set the symbol reference is to be computed
     /// via the GOT. For example when combined with the MO_PCREL_FLAG it should
     /// produce the relocation @got@pcrel. Fixup is VK_PPC_GOT_PCREL.
     MO_GOT_FLAG = 8,
 
+    // MO_PCREL_OPT_FLAG - If this bit is set the operand is part of a
+    // PC Relative linker optimization.
+    MO_PCREL_OPT_FLAG = 16,
+
     /// The next are not flags but distinct values.
     MO_ACCESS_MASK = 0xf00,
 
     /// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
     MO_LO = 1 << 8,
     MO_HA = 2 << 8,
 
     MO_TPREL_LO = 4 << 8,

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 
 ArrayRef<std::pair<unsigned, const char *>>
 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace PPCII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
-      {MO_GOT_FLAG, "ppc-got"}};
+      {MO_GOT_FLAG, "ppc-got"},
+      {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas
 // the FP ones have the advantage of lower latency and higher throughput. So
 // what we are after is using the faster instructions in low register pressure
 // situations and using the larger register file in high register pressure

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   assert((Subtarget->isUsingPCRelativeCalls() || MIOpcode != PPC::BL8_NOTOC) &&
          "BL8_NOTOC is only valid when using PC Relative Calls.");
   if (Subtarget->isUsingPCRelativeCalls()) {
     if (MIOpcode == PPC::TAILB || MIOpcode == PPC::TAILB8 ||
         MIOpcode == PPC::TCRETURNdi || MIOpcode == PPC::TCRETURNdi8 ||
         MIOpcode == PPC::BL8_NOTOC) {
       RefKind = MCSymbolRefExpr::VK_PPC_NOTOC;
     }
+    if (MO.getTargetFlags() == PPCII::MO_PCREL_OPT_FLAG)
+      RefKind = MCSymbolRefExpr::VK_PPC_PCREL_OPT;
   }
 
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
   // If -msecure-plt -fPIC, add 32768 to symbol.
   if (Subtarget->isSecurePlt() && TM.isPositionIndependent() &&
       M->getPICLevel() == PICLevel::BigPIC &&
       MO.getTargetFlags() == PPCII::MO_PLT)
     Expr =
         MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(32768, Ctx), Ctx);
 
   if (!MO.isJTI() && MO.getOffset())
     Expr = MCBinaryExpr::createAdd(Expr,

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

 #include "PPCSubtarget.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-pre-emit-peephole"
 
 STATISTIC(NumRRConvertedInPreEmit,
           "Number of r+r instructions converted to r+i in pre-emit peephole");
 STATISTIC(NumRemovedInPreEmit,
           "Number of instructions deleted in pre-emit peephole");
 STATISTIC(NumberOfSelfCopies,
           "Number of self copy instructions eliminated");
 STATISTIC(NumFrameOffFoldInPreEmit,
           "Number of folding frame offset by using r+r in pre-emit peephole");
 
 static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
 
 namespace {
+
+static bool hasPCRelativeForm(MachineInstr &Use) {
+  switch (Use.getOpcode()) {
+  default:
+    return false;
+  case PPC::LBZ:
+  case PPC::LBZ8:
+  case PPC::LHA:
+  case PPC::LHA8:
+  case PPC::LHZ:
+  case PPC::LHZ8:
+  case PPC::LWZ:
+  case PPC::LWZ8:
+  case PPC::STB:
+  case PPC::STB8:
+  case PPC::STH:
+  case PPC::STH8:
+  case PPC::STW:
+  case PPC::STW8:
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA:
+  case PPC::LXSD:
+  case PPC::LXSSP:
+  case PPC::LXV:
+  case PPC::STXSD:
+  case PPC::STXSSP:
+  case PPC::STXV:
+  case PPC::LFD:
+  case PPC::LFS:
+  case PPC::STFD:
+  case PPC::STFS:
+  case PPC::DFLOADf32:
+  case PPC::DFLOADf64:
+  case PPC::DFSTOREf32:
+  case PPC::DFSTOREf64:
+    return true;
+  }
+}
+
   class PPCPreEmitPeephole : public MachineFunctionPass {
   public:
     static char ID;
     PPCPreEmitPeephole() : MachineFunctionPass(ID) {
       initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry());
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
bool removeRedundantLIs(MachineBasicBlock &MBB,
 
       for (MachineInstr *MI : InstrsToErase) {
         MI->eraseFromParent();
       }
       NumRemovedInPreEmit += InstrsToErase.size();
       return !InstrsToErase.empty();
     }
 
+    // Check if this instruction is a PLDpc that is part of a GOT indirect
+    // access.
+    bool isGOTPLDpc(MachineInstr &Instr) {
+      if (Instr.getOpcode() != PPC::PLDpc)
+        return false;
+
+      // The result must be a register.
+      const MachineOperand &LoadedAddressReg = Instr.getOperand(0);
+      if (!LoadedAddressReg.isReg())
+        return false;
+
+      // Make sure that this is a global symbol.
+      const MachineOperand &SymbolOp = Instr.getOperand(1);
+      if (!SymbolOp.isGlobal())
+        return false;
+
+      // Finally return true only if the GOT flag is present.
+      return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
+    }
+
+    bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
+      MachineFunction *MF = MBB.getParent();
+      // Add this linker opt only if we are using PC Relative memops.
+      if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls())
+        return false;
+
+      // Struct to keep track of one def/use pair for a GOT indirect access.
+      struct GOTDefUsePair {
+        MachineBasicBlock::iterator DefInst;
+        MachineBasicBlock::iterator UseInst;
+        Register DefReg;
+        Register UseReg;
+        bool StillValid;
+      };
+      // Vector of def/ues pairs in this basic block.
+      SmallVector<GOTDefUsePair, 4> CandPairs;
+      SmallVector<GOTDefUsePair, 4> ValidPairs;
+      bool MadeChange = false;
+
+      // Run through all of the instructions in the basic block and try to
+      // collect potential pairs of GOT indirect access instructions.
+      for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
+        // Look for the initial GOT indirect load.
+        if (isGOTPLDpc(*BBI)) {
+          GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(),
+                                    BBI->getOperand(0).getReg(),
+                                    PPC::NoRegister, true};
+          CandPairs.push_back(CurrentPair);
+          continue;
+        }
+
+        // We haven't encountered any new PLD instructions, nothing to check.
+        if (CandPairs.empty())
+          continue;
+
+        // Run through the candidate pairs and see if any of the registers
+        // defined in the PLD instructions are used by this instruction.
+        // Note: the size of CandPairs can change in the loop.
+        for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) {
+          GOTDefUsePair &Pair = CandPairs[Idx];
+          // The instruction does not use or modify this PLD's def reg,
+          // ignore it.
+          if (!BBI->readsRegister(Pair.DefReg, TRI) &&
+              !BBI->modifiesRegister(Pair.DefReg, TRI))
+            continue;
+
+          // The use needs to be used in the address compuation and not
+          // as the register being stored for a store.
+          const MachineOperand *UseOp =
+              hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr;
+
+          // Check for a valid use.
+          if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
+              UseOp->isUse() && UseOp->isKill()) {
+            Pair.UseInst = BBI;
+            Pair.UseReg = BBI->getOperand(0).getReg();
+            ValidPairs.push_back(Pair);
+          }
+          CandPairs.erase(CandPairs.begin() + Idx);
+        }
+      }
+
+      // Go through all of the pairs and check for any more valid uses.
+      for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) {
+        // We shouldn't be here if we don't have a valid pair.
+        assert(Pair->UseInst.isValid() && Pair->StillValid &&
+               "Kept an invalid def/use pair for GOT PCRel opt");
+        // We have found a potential pair. Search through the instructions
+        // between the def and the use to see if it is valid to mark this as a
+        // linker opt.
+        MachineBasicBlock::iterator BBI = Pair->DefInst;
+        ++BBI;
+        for (; BBI != Pair->UseInst; ++BBI) {
+          if (BBI->readsRegister(Pair->UseReg, TRI) ||
+              BBI->modifiesRegister(Pair->UseReg, TRI)) {
+            Pair->StillValid = false;
+            break;
+          }
+        }
+
+        if (!Pair->StillValid)
+          continue;
+
+        // The load/store instruction that uses the address from the PLD will
+        // either use a register (for a store) or define a register (for the
+        // load). That register will be added as an implicit def to the PLD
+        // and as an implicit use on the second memory op. This is a precaution
+        // to prevent future passes from using that register between the two
+        // instructions.
+        MachineOperand ImplDef =
+            MachineOperand::CreateReg(Pair->UseReg, true, true);
+        MachineOperand ImplUse =
+            MachineOperand::CreateReg(Pair->UseReg, false, true);
+        Pair->DefInst->addOperand(ImplDef);
+        Pair->UseInst->addOperand(ImplUse);
+
+        // Create the symbol.
+        MCContext &Context = MF->getContext();
+        MCSymbol *Symbol =
+            Context.createTempSymbol(Twine("pcrel"), false, false);
+        MachineOperand PCRelLabel =
+            MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG);
+        Pair->DefInst->addOperand(*MF, PCRelLabel);
+        Pair->UseInst->addOperand(*MF, PCRelLabel);
+        MadeChange |= true;
+      }
+      return MadeChange;
+    }
+
     bool runOnMachineFunction(MachineFunction &MF) override {
       if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
         // Remove UNENCODED_NOP even when this pass is disabled.
         // This needs to be done unconditionally so we don't emit zeros
         // in the instruction stream.
         SmallVector<MachineInstr *, 4> InstrsToErase;
         for (MachineBasicBlock &MBB : MF)
           for (MachineInstr &MI : MBB)
             if (MI.getOpcode() == PPC::UNENCODED_NOP)
               InstrsToErase.push_back(&MI);
         for (MachineInstr *MI : InstrsToErase)
           MI->eraseFromParent();
         return false;
       }
       bool Changed = false;
       const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
       SmallVector<MachineInstr *, 4> InstrsToErase;
       for (MachineBasicBlock &MBB : MF) {
         Changed |= removeRedundantLIs(MBB, TRI);
+        Changed |= addLinkerOpt(MBB, TRI);
         for (MachineInstr &MI : MBB) {
           unsigned Opc = MI.getOpcode();
           if (Opc == PPC::UNENCODED_NOP) {
             InstrsToErase.push_back(&MI);
             continue;
           }
           // Detect self copies - these can result from running AADB.
           if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll

 ; CHECK-S-NEXT:    std r0, 16(r1)
 ; CHECK-S-NEXT:    stdu r1, -32(r1)
 ; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-S-NEXT:    .cfi_offset lr, 16
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    bl localCall@notoc
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
+; CHECK-S-NEXT: .Lpcrel:
+; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    addi r1, r1, 32
 ; CHECK-S-NEXT:    ld r0, 16(r1)
 ; CHECK-S-NEXT:    mtlr r0
 ; CHECK-S-NEXT:    blr
 entry:

 ; CHECK-S-NEXT:    std r0, 16(r1)
 ; CHECK-S-NEXT:    stdu r1, -32(r1)
 ; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-S-NEXT:    .cfi_offset lr, 16
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    bl externCall@notoc
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel0:
+; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    addi r1, r1, 32
 ; CHECK-S-NEXT:    ld r0, 16(r1)
 ; CHECK-S-NEXT:    mtlr r0
 ; CHECK-S-NEXT:    blr
 entry:
entry:
   ret i32 %call
 }
 
 define dso_local signext i32 @TailCallLocal2(i32 signext %a) local_unnamed_addr {
 ; CHECK-ALL-LABEL: TailCallLocal2:
 ; CHECK-S:         .localentry     TailCallLocal2
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S:         pld r4, externGlobalVar@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel1:
+; CHECK-S-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    b localCall@notoc
 entry:
   %0 = load i32, i32* @externGlobalVar, align 4
   %add = add nsw i32 %0, %a
   %call = tail call signext i32 @localCall(i32 signext %add)
entry:
   ret i32 %call
 }
 
 define dso_local signext i32 @TailCallExtern2(i32 signext %a) local_unnamed_addr {
 ; CHECK-ALL-LABEL: TailCallExtern2:
 ; CHECK-S:         .localentry     TailCallExtern2
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S:         pld r4, externGlobalVar@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel2:
+; CHECK-S-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    b externCall@notoc
 entry:
   %0 = load i32, i32* @externGlobalVar, align 4
   %add = add nsw i32 %0, %a
   %call = tail call signext i32 @externCall(i32 signext %add)

 ; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-S-NEXT:    .cfi_offset lr, 16
 ; CHECK-S-NEXT:    pld r12, indirectCall@PCREL(0), 1
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    mtctr r12
 ; CHECK-S-NEXT:    bctrl
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel3:
+; CHECK-S-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    addi r1, r1, 32
 ; CHECK-S-NEXT:    ld r0, 16(r1)
 ; CHECK-S-NEXT:    mtlr r0
 ; CHECK-S-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll

 @array = external local_unnamed_addr global [10 x i32], align 4
 @structure = external local_unnamed_addr global %struct.Struct, align 4
 @ptrfunc = external local_unnamed_addr global void (...)*, align 8
 
 define dso_local signext i32 @ReadGlobalVarChar() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarChar:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valChar@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel:
+; LE-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; LE-NEXT:    lbz r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarChar:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valChar@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel:
+; BE-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; BE-NEXT:    lbz r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i8, i8* @valChar, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
entry:
   store i8 3, i8* @valChar, align 1
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarShort() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarShort:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valShort@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel0:
+; LE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; LE-NEXT:    lha r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarShort:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valShort@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel0:
+; BE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; BE-NEXT:    lha r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i16, i16* @valShort, align 2
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
entry:
   store i16 3, i16* @valShort, align 2
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarInt:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valInt@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel1:
+; LE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarInt:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valInt@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel1:
+; BE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; BE-NEXT:    lwa r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32, i32* @valInt, align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalVarInt() local_unnamed_addr  {
entry:
   store i32 33, i32* @valInt, align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarUnsigned() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarUnsigned:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel2:
+; LE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarUnsigned:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel2:
+; BE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; BE-NEXT:    lwa r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32, i32* @valUnsigned, align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalVarUnsigned() local_unnamed_addr  {
entry:
   store i32 33, i32* @valUnsigned, align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarLong() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarLong:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valLong@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel3:
+; LE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarLong:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valLong@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel3:
+; BE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; BE-NEXT:    lwa r3, 4(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i64, i64* @valLong, align 8
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
entry:
   store i64 3333, i64* @valLong, align 8
   ret void
 }
 
 define dso_local i32* @ReadGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalPtr:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel4:
+; LE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; LE-NEXT:    ld r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalPtr:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel4:
+; BE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; BE-NEXT:    ld r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32*, i32** @ptr, align 8
   ret i32* %0
 }
 
 define dso_local void @WriteGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalPtr:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel5:
 ; LE-NEXT:    li r4, 3
+; LE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
 ; LE-NEXT:    ld r3, 0(r3)
 ; LE-NEXT:    stw r4, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalPtr:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel5:
 ; BE-NEXT:    li r4, 3
+; BE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
 ; BE-NEXT:    ld r3, 0(r3)
 ; BE-NEXT:    stw r4, 0(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32*, i32** @ptr, align 8
   store i32 3, i32* %0, align 4
   ret void
 }

 entry:
   ret i32* @valInt
 }
 
 define dso_local signext i32 @ReadGlobalArray() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalArray:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, array@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel6:
+; LE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
 ; LE-NEXT:    lwa r3, 12(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalArray:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, array@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel6:
+; BE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
 ; BE-NEXT:    lwa r3, 12(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array, i64 0, i64 3), align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalArray() local_unnamed_addr  {
entry:
   store i32 5, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array, i64 0, i64 3), align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalStruct() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalStruct:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, structure@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel7:
+; LE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
 ; LE-NEXT:    lwa r3, 4(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalStruct:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, structure@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel7:
+; BE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
 ; BE-NEXT:    lwa r3, 4(r3)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32, i32* getelementptr inbounds (%struct.Struct, %struct.Struct* @structure, i64 0, i32 2), align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalStruct() local_unnamed_addr  {
entry:
   ret void
 }
 
 define dso_local void @ReadFuncPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadFuncPtr:
 ; LE:         .localentry ReadFuncPtr, 1
 ; LE-NEXT:  # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
+; LE-NEXT:  .Lpcrel8:
+; LE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
 ; LE-NEXT:    ld r12, 0(r3)
 ; LE-NEXT:    mtctr r12
 ; LE-NEXT:    bctr
 ; LE-NEXT:    #TC_RETURNr8 ctr 0
 ;
 ; BE-LABEL: ReadFuncPtr:
 ; BE:         .localentry ReadFuncPtr, 1
 ; BE-NEXT:  # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
+; BE-NEXT:  .Lpcrel8:
+; BE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
 ; BE-NEXT:    ld r12, 0(r3)
 ; BE-NEXT:    mtctr r12
 ; BE-NEXT:    bctr
 ; BE-NEXT:    #TC_RETURNr8 ctr 0
 entry:
   %0 = load void ()*, void ()** bitcast (void (...)** @ptrfunc to void ()**), align 8
   tail call void %0()
   ret void

llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s
+
+; On future CPU with PC Relative addressing enabled, it is possible for the
+; linker to optimize GOT indirect accesses. In order for the linker to do this
+; the compiler needs to add a hint using the R_PPC64_PCREL_OPT relocation.
+; This test checks that the compiler adds the R_PPC64_PCREL_OPT relocation
+; correctly.
+
+@input8 = external local_unnamed_addr global i8, align 1
+@output8 = external local_unnamed_addr global i8, align 1
+@input16 = external local_unnamed_addr global i16, align 2
+@output16 = external local_unnamed_addr global i16, align 2
+@input32 = external global i32, align 4
+@output32 = external local_unnamed_addr global i32, align 4
+@input64 = external local_unnamed_addr global i64, align 8
+@output64 = external local_unnamed_addr global i64, align 8
+@input128 = external local_unnamed_addr global i128, align 16
+@output128 = external local_unnamed_addr global i128, align 16
+@inputf32 = external local_unnamed_addr global float, align 4
+@outputf32 = external local_unnamed_addr global float, align 4
+@inputf64 = external local_unnamed_addr global double, align 8
+@outputf64 = external local_unnamed_addr global double, align 8
+@inputVi32 = external local_unnamed_addr global <4 x i32>, align 16
+@outputVi32 = external local_unnamed_addr global <4 x i32>, align 16
+@inputVi64 = external local_unnamed_addr global <2 x i64>, align 16
+@outputVi64 = external local_unnamed_addr global <2 x i64>, align 16
+@ArrayIn = external global [10 x i32], align 4
+@ArrayOut = external local_unnamed_addr global [10 x i32], align 4
+@IntPtrIn = external local_unnamed_addr global i32*, align 8
+@IntPtrOut = external local_unnamed_addr global i32*, align 8
+@FuncPtrIn = external local_unnamed_addr global void (...)*, align 8
+@FuncPtrOut = external local_unnamed_addr global void (...)*, align 8
+
+define dso_local void @ReadWrite8() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWrite8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input8@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel:
+; CHECK-NEXT:    pld r4, output8@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-NEXT:    lbz r3, 0(r3)
+; In this test the stb r3, 0(r4) cannot be optimized because it
+; uses the register r3 and that register is defined by lbz r3, 0(r3)
+; which is defined between the pld and the stb.
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i8, i8* @input8, align 1
+  store i8 %0, i8* @output8, align 1
+  ret void
+}
+
+define dso_local void @ReadWrite16() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWrite16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input16@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel0:
+; CHECK-NEXT:    pld r4, output16@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; CHECK-NEXT:    lhz r3, 0(r3)
+; In this test the sth r3, 0(r4) cannot be optimized because it
+; uses the register r3 and that register is defined by lhz r3, 0(r3)
+; which is defined between the pld and the sth.
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i16, i16* @input16, align 2
+  store i16 %0, i16* @output16, align 2
+  ret void
+}
+
+define dso_local void @ReadWrite32() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWrite32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input32@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel1:
+; CHECK-NEXT:    pld r4, output32@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @input32, align 4
+  store i32 %0, i32* @output32, align 4
+  ret void
+}
+
+define dso_local void @ReadWrite64() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWrite64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input64@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel2:
+; CHECK-NEXT:    pld r4, output64@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i64, i64* @input64, align 8
+  store i64 %0, i64* @output64, align 8
+  ret void
+}
+
+; FIXME: we should always convert X-Form instructions that use
+; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
+define dso_local void @ReadWrite128() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWrite128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input128@got@pcrel(0), 1
+; CHECK-NEXT:    lxvx vs0, 0, r3
+; CHECK-NEXT:    pld r3, output128@got@pcrel(0), 1
+; CHECK-NEXT:    stxvx vs0, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i128, i128* @input128, align 16
+  store i128 %0, i128* @output128, align 16
+  ret void
+}
+
+define dso_local void @ReadWritef32() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWritef32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, inputf32@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel3:
+; CHECK-NEXT:    xxspltidp vs1, 1078103900
+; CHECK-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
+; CHECK-NEXT:    lfs f0, 0(r3)
+; CHECK-NEXT:    pld r3, outputf32@got@pcrel(0), 1
+; CHECK-NEXT:    xsaddsp f0, f0, f1
+; CHECK-NEXT:    stfs f0, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load float, float* @inputf32, align 4
+  %add = fadd float %0, 0x400851EB80000000
+  store float %add, float* @outputf32, align 4
+  ret void
+}
+
+define dso_local void @ReadWritef64() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWritef64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, inputf64@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel4:
+; CHECK-NEXT:    plfd f1, .LCPI6_0@PCREL(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
+; CHECK-NEXT:    lfd f0, 0(r3)
+; CHECK-NEXT:    pld r3, outputf64@got@pcrel(0), 1
+; CHECK-NEXT:    xsadddp f0, f0, f1
+; CHECK-NEXT:    stfd f0, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load double, double* @inputf64, align 8
+  %add = fadd double %0, 6.800000e+00
+  store double %add, double* @outputf64, align 8
+  ret void
+}
+
+; FIXME: we should always convert X-Form instructions that use
+; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
+define dso_local void @ReadWriteVi32() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteVi32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, inputVi32@got@pcrel(0), 1
+; CHECK-NEXT:    li r4, 45
+; CHECK-NEXT:    mtfprwz f1, r4
+; CHECK-NEXT:    lxvx vs0, 0, r3
+; CHECK-NEXT:    pld r3, outputVi32@got@pcrel(0), 1
+; CHECK-NEXT:    xxinsertw vs0, vs1, 8
+; CHECK-NEXT:    stxvx vs0, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
+  %vecins = insertelement <4 x i32> %0, i32 45, i32 1
+  store <4 x i32> %vecins, <4 x i32>* @outputVi32, align 16
+  ret void
+}
+
+define dso_local void @ReadWriteVi64() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteVi64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, inputVi64@got@pcrel(0), 1
+; CHECK-NEXT:    lxvx vs0, 0, r3
+; CHECK-NEXT:    pld r3, outputVi64@got@pcrel(0), 1
+; CHECK-NEXT:    stxvx vs0, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <2 x i64>, <2 x i64>* @inputVi64, align 16
+  store <2 x i64> %0, <2 x i64>* @outputVi64, align 16
+  ret void
+}
+
+define dso_local void @ReadWriteArray() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteArray:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, ArrayIn@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel5:
+; CHECK-NEXT:    pld r4, ArrayOut@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
+; CHECK-NEXT:    lwz r3, 28(r3)
+; CHECK-NEXT:    addi r3, r3, 42
+; CHECK-NEXT:    stw r3, 8(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 7), align 4
+  %add = add nsw i32 %0, 42
+  store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayOut, i64 0, i64 2), align 4
+  ret void
+}
+
+define dso_local void @ReadWriteSameArray() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteSameArray:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, ArrayIn@got@pcrel(0), 1
+; CHECK-NEXT:    lwz r4, 12(r3)
+; CHECK-NEXT:    addi r4, r4, 8
+; CHECK-NEXT:    stw r4, 24(r3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 3), align 4
+  %add = add nsw i32 %0, 8
+  store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 6), align 4
+  ret void
+}
+
+define dso_local void @ReadWriteIntPtr() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteIntPtr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, IntPtrIn@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel6:
+; CHECK-NEXT:    pld r4, IntPtrOut@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel7:
+; CHECK-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
+; CHECK-NEXT:    ld r4, 0(r4)
+; CHECK-NEXT:    lwz r5, 216(r3)
+; CHECK-NEXT:    lwz r3, 48(r3)
+; CHECK-NEXT:    add r3, r3, r5
+; CHECK-NEXT:    stw r3, 136(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32*, i32** @IntPtrIn, align 8
+  %arrayidx = getelementptr inbounds i32, i32* %0, i64 54
+  %1 = load i32, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %0, i64 12
+  %2 = load i32, i32* %arrayidx1, align 4
+  %add = add nsw i32 %2, %1
+  %3 = load i32*, i32** @IntPtrOut, align 8
+  %arrayidx2 = getelementptr inbounds i32, i32* %3, i64 34
+  store i32 %add, i32* %arrayidx2, align 4
+  ret void
+}
+
+define dso_local void @ReadWriteFuncPtr() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadWriteFuncPtr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, FuncPtrIn@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel8:
+; CHECK-NEXT:    pld r4, FuncPtrOut@got@pcrel(0), 1
+; CHECK-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i64, i64* bitcast (void (...)** @FuncPtrIn to i64*), align 8
+  store i64 %0, i64* bitcast (void (...)** @FuncPtrOut to i64*), align 8
+  ret void
+}
+
+define dso_local void @FuncPtrCopy() local_unnamed_addr #0 {
+; CHECK-LABEL: FuncPtrCopy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, FuncPtrOut@got@pcrel(0), 1
+; CHECK-NEXT:    pld r4, Callee@got@pcrel(0), 1
+; CHECK-NEXT:    std r4, 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store void (...)* @Callee, void (...)** @FuncPtrOut, align 8
+  ret void
+}
+
+declare void @Callee(...)
+
+define dso_local void @FuncPtrCall() local_unnamed_addr #0 {
+; CHECK-LABEL: FuncPtrCall:
+; CHECK:         .localentry FuncPtrCall, 1
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, FuncPtrIn@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel9:
+; CHECK-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
+; CHECK-NEXT:    ld r12, 0(r3)
+; CHECK-NEXT:    mtctr r12
+; CHECK-NEXT:    bctr
+; CHECK-NEXT:    #TC_RETURNr8 ctr 0
+entry:
+  %0 = load void ()*, void ()** bitcast (void (...)** @FuncPtrIn to void ()**), align 8
+  tail call void %0()
+  ret void
+}
+
+define dso_local signext i32 @ReadVecElement() local_unnamed_addr #0 {
+; CHECK-LABEL: ReadVecElement:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, inputVi32@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel10:
+; CHECK-NEXT:    .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8)
+; CHECK-NEXT:    lwa r3, 4(r3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
+  %vecext = extractelement <4 x i32> %0, i32 1
+  ret i32 %vecext
+}
+
+define dso_local signext i32 @VecMultiUse() local_unnamed_addr #0 {
+; CHECK-LABEL: VecMultiUse:
+; CHECK:         .localentry VecMultiUse, 1
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    pld r30, inputVi32@got@pcrel(0), 1
+; CHECK-NEXT:    lwz r29, 4(r30)
+; CHECK-NEXT:    bl Callee@notoc
+; CHECK-NEXT:    lwz r3, 8(r30)
+; CHECK-NEXT:    add r29, r3, r29
+; CHECK-NEXT:    bl Callee@notoc
+; CHECK-NEXT:    lwz r3, 0(r30)
+; CHECK-NEXT:    add r3, r29, r3
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    addi r1, r1, 64
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
+  tail call void bitcast (void (...)* @Callee to void ()*)()
+  %1 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
+  %2 = extractelement <4 x i32> %1, i32 2
+  %3 = extractelement <4 x i32> %0, i64 1
+  %4 = add nsw i32 %2, %3
+  tail call void bitcast (void (...)* @Callee to void ()*)()
+  %5 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
+  %vecext2 = extractelement <4 x i32> %5, i32 0
+  %add3 = add nsw i32 %4, %vecext2
+  ret i32 %add3
+}
+
+define dso_local signext i32 @UseAddr(i32 signext %a) local_unnamed_addr #0 {
+; CHECK-LABEL: UseAddr:
+; CHECK:         .localentry UseAddr, 1
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    pld r4, ArrayIn@got@pcrel(0), 1
+; CHECK-NEXT:    lwz r5, 16(r4)
+; CHECK-NEXT:    add r30, r5, r3
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    bl getAddr@notoc
+; CHECK-NEXT:    add r3, r30, r3
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    addi r1, r1, 48
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 4), align 4
+  %add = add nsw i32 %0, %a
+  %call = tail call signext i32 @getAddr(i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 0))
+  %add1 = add nsw i32 %add, %call
+  ret i32 %add1
+}
+
+declare signext i32 @getAddr(i32*) local_unnamed_addr
+
+define dso_local nonnull i32* @AddrTaken32() local_unnamed_addr #0 {
+; CHECK-LABEL: AddrTaken32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pld r3, input32@got@pcrel(0), 1
+; CHECK-NEXT:    blr
+entry:
+  ret i32* @input32
+}
+
+attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll

entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array2, i64 0, i64 -2), align 4
   ret i32 %0
 }
 
 define dso_local signext i32 @getElementExtern4() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementExtern4:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, array1@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel:
+; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; CHECK-S-NEXT:    lwa r3, 16(r3)
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementExtern4>:
 ; CHECK-O:         pld 3, 0(0), 1
 ; CHECK-O-NEXT:      R_PPC64_GOT_PCREL34  array1
-; CHECK-O-NEXT:    lwa 3, 16(3)
+; CHECK-O-NEXT:      R_PPC64_PCREL_OPT *ABS*+0x8
+; CHECK-O:         lwa 3, 16(3)
 ; CHECK-O-NEXT:    blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array1, i64 0, i64 4), align 4
   ret i32 %0
 }
 
 define dso_local signext i32 @getElementExternNegative() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementExternNegative:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, array1@got@pcrel(0), 1
+; CHECK-S-NEXT:  .Lpcrel0:
+; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-S-NEXT:    lwa r3, -4(r3)
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementExternNegative>:
 ; CHECK-O:         pld 3, 0(0), 1
 ; CHECK-O-NEXT:      R_PPC64_GOT_PCREL34  array1
-; CHECK-O-NEXT:    lwa 3, -4(3)
+; CHECK-O-NEXT:      R_PPC64_PCREL_OPT *ABS*+0x8
+; CHECK-O:         lwa 3, -4(3)
 ; CHECK-O-NEXT:    blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array1, i64 0, i64 -1), align 4
   ret i32 %0
 }
 
 

llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll

entry:
   ret void
 }
 
 define dso_local void @TailCallExtrnFuncPtr() local_unnamed_addr {
 ; CHECK-LABEL: TailCallExtrnFuncPtr:
 ; CHECK:         .localentry TailCallExtrnFuncPtr, 1
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, Func@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel:
+; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    mtctr r12
 ; CHECK-NEXT:    bctr
 ; CHECK-NEXT:    #TC_RETURNr8 ctr 0
 entry:
   %0 = load i32 ()*, i32 ()** bitcast (i32 (...)** @Func to i32 ()**), align 8
   %call = tail call signext i32 %0()
   ret void

llvm/test/CodeGen/PowerPC/pcrel.ll

entry:
   ret i32 %0
 }
 
 @valIntGlob = external global i32, align 4
 define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr  {
 ; CHECK-S-LABEL: ReadGlobalVarInt
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, valIntGlob@got@pcrel(0), 1
+; CHECK-S-NEXT: .Lpcrel:
+; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
 ; CHECK-S-NEXT:    lwa r3, 0(r3)
 ; CHECK-S-NEXT:    blr
 
 ; CHECK-O-LABEL: ReadGlobalVarInt
 ; CHECK-O:         pld 3, 0(0), 1
 ; CHECK-O-NEXT:    R_PPC64_GOT_PCREL34 valIntGlob
+; CHECK-O-NEXT:    R_PPC64_PCREL_OPT *ABS*+0x8
 ; CHECK-O-NEXT:    lwa 3, 0(3)
 ; CHECK-O-NEXT:    blr
 entry:
   %0 = load i32, i32* @valIntGlob, align 4
   ret i32 %0
 }