A linker optimization is available on PowerPC for GOT indirect PCRelative loads.
When the compiler generates a GOT indirect load it must generate two loads. One
that loads the address of the element from the GOT and a second to load the
actual element based on the address just loaded from the GOT. However, the
linker can optimize these two loads into one load if it knows that it is safe
to do so. The compiler can tell the linker that the optimization is safe
by using the R_PPC64_PCREL_OPT relocation. The relocation can be used as follows
pld 3, vec@got@pcrel(0), 1 .Lpcrel1: ... More instructions possible here ... .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8) lwa 3, 4(3)
The first load to get the address from the GOT has a label immediately following
it (in this case Lpcrel1) and then the second load has the .reloc directive that
actually attaches the relocation to the first load using the Lpcrel1-8. The end
result is that the first load from the GOT has a relocation on it that specifies
the offset in the text section to the second load so that the linker can perform
There is another possible form for this setup as follows:
pld 3, vec@got@pcrel(0), 1 .Lpcrel1=.-8 ... More instructions possible here ... .reloc .Lpcrel1,R_PPC64_PCREL_OPT,.-.Lpcrel1 lwa 3, 4(3)
In the second form the label is variable and contains the .-8.
This patch expands the .reloc directive to support the second form from above. The first form was added in D83751.