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Differential D77867

[RISCV][AsmParser] Implement .option (no)pic
ClosedPublic

Authored by rogfer01 on Apr 10 2020, 5:54 AM.

Details

Reviewers
asb
luismarques
jrtc27
lewis-revill
lenary
Commits
rG5f236864124d: [RISCV][AsmParser] Implement .option (no)pic
Summary

This directive impacts assembly pseudoinstruction la.

Also add a test for codegen to assert that this directive behaves like other ones (i.e. no effect) when directly emitting ELF files from codegen.

Diff Detail

Event Timeline

rogfer01 created this revision.Apr 10 2020, 5:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 10 2020, 5:54 AM
Herald added subscribers: llvm-commits, evandro, apazos and 24 others. · View Herald Transcript
Harbormaster failed remote builds in B52661: Diff 256553!Apr 10 2020, 6:52 AM
lenary accepted this revision.Apr 13 2020, 6:38 AM

LGTM, Thanks!

This revision is now accepted and ready to land.Apr 13 2020, 6:38 AM
rogfer01 added a comment.Apr 17 2020, 5:14 AM

Thanks for the review @lenary!

Closed by commit rG5f236864124d: [RISCV][AsmParser] Implement .option (no)pic (authored by rogfer01). · Explain WhyApr 17 2020, 5:22 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
AsmParser/
45 lines
MCTargetDesc/
2 lines
2 lines
4 lines
8 lines
test/
CodeGen/
RISCV/
18 lines
17 lines
MC/
RISCV/
29 lines
28 lines
42 lines

Diff 258295

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
#include "RISCVGenCompressInstEmitter.inc" #include "RISCVGenCompressInstEmitter.inc"
STATISTIC(RISCVNumInstrsCompressed, STATISTIC(RISCVNumInstrsCompressed,
"Number of RISC-V Compressed instructions emitted"); "Number of RISC-V Compressed instructions emitted");
namespace { namespace {
struct RISCVOperand; struct RISCVOperand;
struct ParserOptionsSet {
bool IsPicEnabled;
};
class RISCVAsmParser : public MCTargetAsmParser { class RISCVAsmParser : public MCTargetAsmParser {
SmallVector<FeatureBitset, 4> FeatureBitStack; SmallVector<FeatureBitset, 4> FeatureBitStack;
SmallVector<ParserOptionsSet, 4> ParserOptionsStack;
ParserOptionsSet ParserOptions;
SMLoc getLoc() const { return getParser().getTok().getLoc(); } SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); }
RISCVTargetStreamer &getTargetStreamer() { RISCVTargetStreamer &getTargetStreamer() {
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
return static_cast<RISCVTargetStreamer &>(TS); return static_cast<RISCVTargetStreamer &>(TS);
} }
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (getSTI().getFeatureBits()[Feature]) { if (getSTI().getFeatureBits()[Feature]) {
MCSubtargetInfo &STI = copySTI(); MCSubtargetInfo &STI = copySTI();
setAvailableFeatures( setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
} }
} }
void pushFeatureBits() { void pushFeatureBits() {
assert(FeatureBitStack.size() == ParserOptionsStack.size() &&
"These two stacks must be kept synchronized");
FeatureBitStack.push_back(getSTI().getFeatureBits()); FeatureBitStack.push_back(getSTI().getFeatureBits());
ParserOptionsStack.push_back(ParserOptions);
} }
bool popFeatureBits() { bool popFeatureBits() {
assert(FeatureBitStack.size() == ParserOptionsStack.size() &&
"These two stacks must be kept synchronized");
if (FeatureBitStack.empty()) if (FeatureBitStack.empty())
return true; return true;
FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); FeatureBitset FeatureBits = FeatureBitStack.pop_back_val();
copySTI().setFeatureBits(FeatureBits); copySTI().setFeatureBits(FeatureBits);
setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); setAvailableFeatures(ComputeAvailableFeatures(FeatureBits));
ParserOptions = ParserOptionsStack.pop_back_val();
return false; return false;
} }
public: public:
enum RISCVMatchResultTy { enum RISCVMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY, Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
#define GET_OPERAND_DIAGNOSTIC_TYPES #define GET_OPERAND_DIAGNOSTIC_TYPES
#include "RISCVGenAsmMatcher.inc" #include "RISCVGenAsmMatcher.inc"
#undef GET_OPERAND_DIAGNOSTIC_TYPES #undef GET_OPERAND_DIAGNOSTIC_TYPES
}; };
Show All 17 Lines if (ABIName.endswith("f") &&
"doesn't support the F instruction set extension (ignoring " "doesn't support the F instruction set extension (ignoring "
"target-abi)\n"; "target-abi)\n";
} else if (ABIName.endswith("d") && } else if (ABIName.endswith("d") &&
!getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {
errs() << "Hard-float 'd' ABI can't be used for a target that " errs() << "Hard-float 'd' ABI can't be used for a target that "
"doesn't support the D instruction set extension (ignoring " "doesn't support the D instruction set extension (ignoring "
"target-abi)\n"; "target-abi)\n";
} }
const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo();
ParserOptions.IsPicEnabled = MOFI->isPositionIndependent();
} }
}; };
/// RISCVOperand - Instances of this class represent a parsed machine /// RISCVOperand - Instances of this class represent a parsed machine
/// instruction /// instruction
struct RISCVOperand : public MCParsedAsmOperand { struct RISCVOperand : public MCParsedAsmOperand {
enum class KindTy { enum class KindTy {
▲ Show 20 Lines • Show All 1,436 Lines • ▼ Show 20 Lines if (Option == "norvc") {
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) if (Parser.getTok().isNot(AsmToken::EndOfStatement))
return Error(Parser.getTok().getLoc(), return Error(Parser.getTok().getLoc(),
"unexpected token, expected end of statement"); "unexpected token, expected end of statement");
clearFeatureBits(RISCV::FeatureStdExtC, "c"); clearFeatureBits(RISCV::FeatureStdExtC, "c");
return false; return false;
} }
if (Option == "pic") {
getTargetStreamer().emitDirectiveOptionPIC();
Parser.Lex();
if (Parser.getTok().isNot(AsmToken::EndOfStatement))
return Error(Parser.getTok().getLoc(),
"unexpected token, expected end of statement");
ParserOptions.IsPicEnabled = true;
return false;
}
if (Option == "nopic") {
getTargetStreamer().emitDirectiveOptionNoPIC();
Parser.Lex();
if (Parser.getTok().isNot(AsmToken::EndOfStatement))
return Error(Parser.getTok().getLoc(),
"unexpected token, expected end of statement");
ParserOptions.IsPicEnabled = false;
return false;
}
if (Option == "relax") { if (Option == "relax") {
getTargetStreamer().emitDirectiveOptionRelax(); getTargetStreamer().emitDirectiveOptionRelax();
Parser.Lex(); Parser.Lex();
if (Parser.getTok().isNot(AsmToken::EndOfStatement)) if (Parser.getTok().isNot(AsmToken::EndOfStatement))
return Error(Parser.getTok().getLoc(), return Error(Parser.getTok().getLoc(),
"unexpected token, expected end of statement"); "unexpected token, expected end of statement");
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Linesvoid RISCVAsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc,
// ADDI rdest, rdest, %pcrel_lo(TmpLabel) // ADDI rdest, rdest, %pcrel_lo(TmpLabel)
// or (for PIC) // or (for PIC)
// TmpLabel: AUIPC rdest, %got_pcrel_hi(symbol) // TmpLabel: AUIPC rdest, %got_pcrel_hi(symbol)
// Lx rdest, %pcrel_lo(TmpLabel)(rdest) // Lx rdest, %pcrel_lo(TmpLabel)(rdest)
MCOperand DestReg = Inst.getOperand(0); MCOperand DestReg = Inst.getOperand(0);
const MCExpr *Symbol = Inst.getOperand(1).getExpr(); const MCExpr *Symbol = Inst.getOperand(1).getExpr();
unsigned SecondOpcode; unsigned SecondOpcode;
RISCVMCExpr::VariantKind VKHi; RISCVMCExpr::VariantKind VKHi;
// FIXME: Should check .option (no)pic when implemented if (ParserOptions.IsPicEnabled) {
if (getContext().getObjectFileInfo()->isPositionIndependent()) {
SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
VKHi = RISCVMCExpr::VK_RISCV_GOT_HI; VKHi = RISCVMCExpr::VK_RISCV_GOT_HI;
} else { } else {
SecondOpcode = RISCV::ADDI; SecondOpcode = RISCV::ADDI;
VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI; VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI;
} }
emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out); emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out);
} }
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Linesprivate:
size_t calculateContentSize() const; size_t calculateContentSize() const;
public: public:
MCELFStreamer &getStreamer(); MCELFStreamer &getStreamer();
RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI); RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
void emitDirectiveOptionPush() override; void emitDirectiveOptionPush() override;
void emitDirectiveOptionPop() override; void emitDirectiveOptionPop() override;
void emitDirectiveOptionPIC() override;
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override; void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override; void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override; void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override; void emitDirectiveOptionNoRelax() override;
}; };
} }
#endif #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
} }
MCELFStreamer &RISCVTargetELFStreamer::getStreamer() { MCELFStreamer &RISCVTargetELFStreamer::getStreamer() {
return static_cast<MCELFStreamer &>(Streamer); return static_cast<MCELFStreamer &>(Streamer);
} }
void RISCVTargetELFStreamer::emitDirectiveOptionPush() {} void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
void RISCVTargetELFStreamer::emitDirectiveOptionPop() {} void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {} void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {} void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {} void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {} void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) { void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true); setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true);
} }
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

Show All 15 Lines
class RISCVTargetStreamer : public MCTargetStreamer { class RISCVTargetStreamer : public MCTargetStreamer {
public: public:
RISCVTargetStreamer(MCStreamer &S); RISCVTargetStreamer(MCStreamer &S);
void finish() override; void finish() override;
virtual void emitDirectiveOptionPush() = 0; virtual void emitDirectiveOptionPush() = 0;
virtual void emitDirectiveOptionPop() = 0; virtual void emitDirectiveOptionPop() = 0;
virtual void emitDirectiveOptionPIC() = 0;
virtual void emitDirectiveOptionNoPIC() = 0;
virtual void emitDirectiveOptionRVC() = 0; virtual void emitDirectiveOptionRVC() = 0;
virtual void emitDirectiveOptionNoRVC() = 0; virtual void emitDirectiveOptionNoRVC() = 0;
virtual void emitDirectiveOptionRelax() = 0; virtual void emitDirectiveOptionRelax() = 0;
virtual void emitDirectiveOptionNoRelax() = 0; virtual void emitDirectiveOptionNoRelax() = 0;
virtual void emitAttribute(unsigned Attribute, unsigned Value) = 0; virtual void emitAttribute(unsigned Attribute, unsigned Value) = 0;
virtual void finishAttributeSection() = 0; virtual void finishAttributeSection() = 0;
virtual void emitTextAttribute(unsigned Attribute, StringRef String) = 0; virtual void emitTextAttribute(unsigned Attribute, StringRef String) = 0;
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
Show All 12 Linesclass RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue) override; StringRef StringValue) override;
public: public:
RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS); RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
void emitDirectiveOptionPush() override; void emitDirectiveOptionPush() override;
void emitDirectiveOptionPop() override; void emitDirectiveOptionPop() override;
void emitDirectiveOptionPIC() override;
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override; void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override; void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override; void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override; void emitDirectiveOptionNoRelax() override;
}; };
} }
#endif #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
void RISCVTargetAsmStreamer::emitDirectiveOptionPush() { void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
OS << "\t.option\tpush\n"; OS << "\t.option\tpush\n";
} }
void RISCVTargetAsmStreamer::emitDirectiveOptionPop() { void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
OS << "\t.option\tpop\n"; OS << "\t.option\tpop\n";
} }
void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
OS << "\t.option\tpic\n";
}
void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
OS << "\t.option\tnopic\n";
}
void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() { void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
OS << "\t.option\trvc\n"; OS << "\t.option\trvc\n";
} }
void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() { void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n"; OS << "\t.option\tnorvc\n";
} }
Show All 22 Lines

llvm/test/CodeGen/RISCV/option-nopic.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -filetype=obj --relocation-model=pic < %s\
; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\
; RUN: | FileCheck -check-prefix=CHECK %s
; This test demonstrates that .option nopic has no effect on codegen when
; emitting an ELF directly.
@symbol = global i32 zeroinitializer
define i32 @get_symbol() nounwind {
; CHECK-LABEL: <get_symbol>:
; CHECK: auipc a0, 0
; CHECK: lw a0, 0(a0)
; CHECK: lw a0, 0(a0)
tail call void asm sideeffect ".option nopic", ""()
%v = load i32, i32* @symbol
ret i32 %v
}

llvm/test/CodeGen/RISCV/option-pic.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -filetype=obj < %s\
; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\
; RUN: | FileCheck -check-prefix=CHECK %s
; This test demonstrates that .option pic has no effect on codegen when
; emitting an ELF directly.
@symbol = global i32 zeroinitializer
define i32 @get_symbol() nounwind {
; CHECK-LABEL: <get_symbol>:
; CHECK: lui a0, 0
; CHECK: lw a0, 0(a0)
tail call void asm sideeffect ".option pic", ""()
%v = load i32, i32* @symbol
ret i32 %v
}

llvm/test/MC/RISCV/option-nopic.s

  • This file was added.
# RUN: llvm-mc -triple riscv32 -mattr=-relax -riscv-no-aliases < %s \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv32 -mattr=-relax -riscv-no-aliases \
# RUN: -position-independent < %s | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -position-independent < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases < %s \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases \
# RUN: -position-independent < %s | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -position-independent < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
.option nopic
# CHECK-INST: .option nopic
la s0, symbol
# CHECK-INST: auipc s0, %pcrel_hi(symbol)
# CHECK-INST: addi s0, s0, %pcrel_lo(.Lpcrel_hi0)
# CHECK-RELOC: R_RISCV_PCREL_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0

llvm/test/MC/RISCV/option-pic.s

  • This file was added.
# RUN: llvm-mc -triple riscv32 -mattr=-relax -riscv-no-aliases < %s \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv32 -mattr=-relax -riscv-no-aliases \
# RUN: -position-independent < %s | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -position-independent < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases < %s \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
# RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases \
# RUN: -position-independent < %s | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -position-independent < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
.option pic
# CHECK-INST: .option pic
la s0, symbol
# CHECK-INST: auipc s0, %got_pcrel_hi(symbol)
# CHECK-INST: l{{[wd]}} s0, %pcrel_lo(.Lpcrel_hi0)(s0)
# CHECK-RELOC: R_RISCV_GOT_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0

llvm/test/MC/RISCV/option-pushpop.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
# CHECK-RELOC: R_RISCV_CALL baz 0x0 # CHECK-RELOC: R_RISCV_CALL baz 0x0
# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0 # CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
call baz call baz
# CHECK-INST: addi s0, sp, 1020 # CHECK-INST: addi s0, sp, 1020
# CHECK-BYTES: 13 04 c1 3f # CHECK-BYTES: 13 04 c1 3f
# CHECK-ALIAS: addi s0, sp, 1020 # CHECK-ALIAS: addi s0, sp, 1020
addi s0, sp, 1020 addi s0, sp, 1020
.option push # Push pic=false
# CHECK-INST: .option push
.option pic
# CHECK-INST: .option pic
la s0, symbol
# CHECK-INST: auipc s0, %got_pcrel_hi(symbol)
# CHECK-INST: l{{[wd]}} s0, %pcrel_lo(.Lpcrel_hi0)(s0)
# CHECK-RELOC: R_RISCV_GOT_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0
.option push # Push pic=true
# CHECK-INST: .option push
.option nopic
# CHECK-INST: .option nopic
la s0, symbol
# CHECK-INST: auipc s0, %pcrel_hi(symbol)
# CHECK-INST: addi s0, s0, %pcrel_lo(.Lpcrel_hi1)
# CHECK-RELOC: R_RISCV_PCREL_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi1 0x0
.option pop # Push pic=true
# CHECK-INST: .option pop
la s0, symbol
# CHECK-INST: auipc s0, %got_pcrel_hi(symbol)
# CHECK-INST: l{{[wd]}} s0, %pcrel_lo(.Lpcrel_hi2)(s0)
# CHECK-RELOC: R_RISCV_GOT_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi2 0x0
.option pop # Push pic=false
# CHECK-INST: .option pop
la s0, symbol
# CHECK-INST: auipc s0, %pcrel_hi(symbol)
# CHECK-INST: addi s0, s0, %pcrel_lo(.Lpcrel_hi3)
# CHECK-RELOC: R_RISCV_PCREL_HI20 symbol 0x0
# CHECK-RELOC: R_RISCV_PCREL_LO12_I .Lpcrel_hi3 0x0