Page MenuHomePhabricator

[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
ClosedPublic

Authored by simon_tatham on Feb 10 2020, 8:54 AM.

Details

Summary

These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.

Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.

The output of one existing codegen test is improved by those new
rules.

This commit adds the unpredicated forms only.

Diff Detail

Event Timeline

simon_tatham created this revision.Feb 10 2020, 8:54 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptFeb 10 2020, 8:54 AM

Spotted a mistake by myself: one of my new isel patterns was generating signed VMOVL where it should have been generating unsigned. Fixed, and updated the llc test that had the wrong expectation in it.

Also rebased to current master.

Cosmetic tweak: don't put the new arm_mve.td section in between the definition and the uses of an unrelated multiclass.

dmgreen accepted this revision.Feb 12 2020, 9:56 AM

I think these odd shuffle then extend patterns might come up in codegen too, so this looks like a nice change.

LGTM, if the test is just a test case problem.

llvm/lib/Target/ARM/ARMInstrMVE.td
2397

Perhaps move this down to outside of the let Predicates = [HasMVEInt] in block?

I also like it when Pats make it obvious what the input and the output are:

def : Pat<(ARMvbicImm (v8i16 (bitconvert (ARMvrev16 (v16i8 MQPR:$src)))),
                      (i32 0xAFF)),
          (MVE_VMOVLu8th MQPR:$src)>;

Those are just minor Nitpicks though.

llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
40

vmovlt.u16? Does this need updating like the others?

This revision is now accepted and ready to land.Feb 12 2020, 9:56 AM

Made the new isel patterns work in big-endian as well as little. Depends on the extra preparatory patch D74716.

dmgreen accepted this revision.Feb 17 2020, 7:38 AM

Nice one.