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[ARM,MVE] Add the vrev16q, vrev32q, vrev64q family.
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Authored by simon_tatham on Feb 10 2020, 8:53 AM.

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Summary

These intrinsics just reorder the lanes of a vector, so the natural IR
representation is as a shufflevector operation. Existing LLVM codegen
already recognizes those particular shufflevectors and generates the
MVE VREV instruction.

This commit adds the unpredicated forms only.

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