[llvm] NFC: Fix trivial typos in comments

[jhenderson]

LGTM, with one nit.

llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp

1

Whilst you're here, can you remove the extra space after "printer" please.

[kiszk]

llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp

1

Sure, I will do it soon.

[kiszk]

• address review comment

[kiszk]

I do not have commit rights to the repository. Could someone commit this change if it is OK?
Kazuaki Ishizaki <[e-mail]>

[jhenderson]

In D72143#1802934, @kiszk wrote:

I do not have commit rights to the repository. Could someone commit this change if it is OK?
Kazuaki Ishizaki <[e-mail]>

Sure, assuming nobody else does before then, I'll commit on Monday.

llvm/bindings/ocaml/llvm/llvm.mli

 val const_shufflevector : llvalue -> llvalue -> llvalue -> llvalue
 
 (** [const_extractvalue agg idxs] returns the constant [idxs]th value of
     constant aggregate [agg]. Each [idxs] must be less than the size of the
     aggregate.  See the method [llvm::ConstantExpr::getExtractValue]. *)
 val const_extractvalue : llvalue -> int array -> llvalue
 
 (** [const_insertvalue agg val idxs] inserts the value [val] in the specified
-    indexs [idxs] in the aggegate [agg]. Each [idxs] must be less than the size
+    indexs [idxs] in the aggregate [agg]. Each [idxs] must be less than the size
     of the aggregate. See the method [llvm::ConstantExpr::getInsertValue]. *)
 val const_insertvalue : llvalue -> llvalue -> int array -> llvalue
 
 (** [const_inline_asm ty asm con side align] inserts a inline assembly string.
     See the method [llvm::InlineAsm::get]. *)
 val const_inline_asm : lltype -> string -> string -> bool -> bool -> llvalue
 
 (** [block_address f bb] returns the address of the basic block [bb] in the

llvm/include/llvm/ADT/PointerUnion.h

namespace pointer_union_detail {
   /// for the template arguments.
   template <typename ...PTs> class PointerUnionUIntTraits {
   public:
     static inline void *getAsVoidPointer(void *P) { return P; }
     static inline void *getFromVoidPointer(void *P) { return P; }
     static constexpr int NumLowBitsAvailable = lowBitsAvailable<PTs...>();
   };
 
-  /// Implement assigment in terms of construction.
+  /// Implement assignment in terms of construction.
   template <typename Derived, typename T> struct AssignableFrom {
     Derived &operator=(T t) {
       return static_cast<Derived &>(*this) = Derived(t);
     }
   };
 
   template <typename Derived, typename ValTy, int I, typename ...Types>
   class PointerUnionMembers;

llvm/include/llvm/Analysis/ValueTracking.h

class Value;
   /// If the specified value can be set by repeating the same byte in memory,
   /// return the i8 value that it is represented with. This is true for all i8
   /// values obviously, but is also true for i32 0, i32 -1, i16 0xF0F0, double
   /// 0.0 etc. If the value can't be handled with a repeated byte store (e.g.
   /// i16 0x1234), return null. If the value is entirely undef and padding,
   /// return undef.
   Value *isBytewiseValue(Value *V, const DataLayout &DL);
 
-  /// Given an aggregrate and an sequence of indices, see if the scalar value
+  /// Given an aggregate and an sequence of indices, see if the scalar value
   /// indexed is already around as a register, for example if it were inserted
-  /// directly into the aggregrate.
+  /// directly into the aggregate.
   ///
   /// If InsertBefore is not null, this function will duplicate (modified)
   /// insertvalues when a part of a nested struct is extracted.
   Value *FindInsertedValue(Value *V,
                            ArrayRef<unsigned> idx_range,
                            Instruction *InsertBefore = nullptr);
 
   /// Analyze the specified pointer to see if it can be expressed as a base

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

struct CallLoweringInfo {
     /// True if the call is to a vararg function.
     bool IsVarArg = false;
   };
 
   /// Argument handling is mostly uniform between the four places that
   /// make these decisions: function formal arguments, call
   /// instruction args, call instruction returns and function
   /// returns. However, once a decision has been made on where an
-  /// arugment should go, exactly what happens can vary slightly. This
+  /// argument should go, exactly what happens can vary slightly. This
   /// class abstracts the differences.
   struct ValueHandler {
     ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
                  CCAssignFn *AssignFn)
       : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
 
     virtual ~ValueHandler() = default;
 

llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h

 /// address range. If a function has discontiguous address ranges, they will
 /// need to be encoded using multiple FunctionInfo objects.
 ///
 /// ENCODING
 ///
 /// The function information gets the function start address as an argument
 /// to the FunctionInfo::decode(...) function. This information is calculated
 /// from the GSYM header and an address offset from the GSYM address offsets
-/// table. The encoded FunctionInfo information must be alinged to a 4 byte
+/// table. The encoded FunctionInfo information must be aligned to a 4 byte
 /// boundary.
 ///
 /// The encoded data for a FunctionInfo starts with fixed data that all
 /// function info objects have:
 ///
 /// ENCODING  NAME        DESCRIPTION
 /// ========= =========== ====================================================
 /// uint32_t  Size        The size in bytes of this function.

llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h

 /// of Header.NumAddresses address offsets. These offsets are sorted and can be
 /// binary searched for efficient lookups. Addresses in the address table are
 /// stored as offsets from a 64 bit base address found in Header.BaseAddress.
 /// This allows the address table to contain 8, 16, or 32 offsets. This allows
 /// the address table to not require full 64 bit addresses for each address.
 /// The resulting GSYM size is smaller and causes fewer pages to be touched
 /// during address lookups when the address table is smaller. The size of the
 /// address offsets in the address table is specified in the header in
-/// Header.AddrOffSize. The first offset in the address table is alinged to
-/// Header.AddrOffSize alignement to ensure efficient access when loaded into
+/// Header.AddrOffSize. The first offset in the address table is aligned to
+/// Header.AddrOffSize alignment to ensure efficient access when loaded into
 /// memory.
 ///
 /// FUNCTION INFO OFFSETS TABLE
 ///
 /// The function info offsets table immediately follows the address table and
 /// consists of Header.NumAddresses 32 bit file offsets: one for each address
-/// in the address table. This data is algined to a 4 byte boundary. The
+/// in the address table. This data is aligned to a 4 byte boundary. The
 /// offsets in this table are the relative offsets from the start offset of the
 /// GSYM header and point to the function info data for each address in the
 /// address table. Keeping this data separate from the address table helps to
 /// reduce the number of pages that are touched when address lookups occur on a
 /// GSYM file.
 ///
 /// FILE TABLE
 ///

llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h

 #include <algorithm>
 #include <cstdint>
 
 namespace llvm {
 namespace orc {
 
 /// Generic ORC ABI support.
 ///
-/// This class can be substituted as the target architecure support class for
+/// This class can be substituted as the target architecture support class for
 /// ORC templates that require one (e.g. IndirectStubsManagers). It does not
 /// support lazy JITing however, and any attempt to use that functionality
 /// will result in execution of an llvm_unreachable.
 class OrcGenericABI {
 public:
   static const unsigned PointerSize = sizeof(uintptr_t);
   static const unsigned TrampolineSize = 1;
   static const unsigned ResolverCodeSize = 1;

llvm/include/llvm/IR/InstrTypes.h

for (unsigned i = 0, e = getNumOperandBundles(); i != e; ++i) {
         return true;
     }
     return false;
   }
 
   /// Is the function attribute S disallowed by some operand bundle on
   /// this operand bundle user?
   bool isFnAttrDisallowedByOpBundle(StringRef S) const {
-    // Operand bundles only possibly disallow readnone, readonly and argmenonly
+    // Operand bundles only possibly disallow readnone, readonly and argmemonly
     // attributes.  All String attributes are fine.
     return false;
   }
 
   /// Is the function attribute A disallowed by some operand bundle on
   /// this operand bundle user?
   bool isFnAttrDisallowedByOpBundle(Attribute::AttrKind A) const {
     switch (A) {

llvm/include/llvm/Support/Allocator.h

#endif
     CurPtr = AlignedPtr + SizeToAllocate;
     __msan_allocated_memory(AlignedPtr, Size);
     __asan_unpoison_memory_region(AlignedPtr, Size);
     return AlignedPtr;
   }
 
   inline LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void *
   Allocate(size_t Size, size_t Alignment) {
-    assert(Alignment > 0 && "0-byte alignnment is not allowed. Use 1 instead.");
+    assert(Alignment > 0 && "0-byte alignment is not allowed. Use 1 instead.");
     return Allocate(Size, Align(Alignment));
   }
 
   // Pull in base class overloads.
   using AllocatorBase<BumpPtrAllocatorImpl>::Allocate;
 
   // Bump pointer allocators are expected to never free their storage; and
   // clients expect pointers to remain valid for non-dereferencing uses even

llvm/include/llvm/Target/Target.td

class AsmParser {
 
   // HasMnemonicFirst - Set to false if target instructions don't always
   // start with a mnemonic as the first token.
   bit HasMnemonicFirst = 1;
 
   // ReportMultipleNearMisses -
   // When 0, the assembly matcher reports an error for one encoding or operand
   // that did not match the parsed instruction.
-  // When 1, the assmebly matcher returns a list of encodings that were close
+  // When 1, the assembly matcher returns a list of encodings that were close
   // to matching the parsed instruction, so to allow more detailed error
   // messages.
   bit ReportMultipleNearMisses = 0;
 }
 def DefaultAsmParser : AsmParser;
 
 //===----------------------------------------------------------------------===//
 // AsmParserVariant - Subtargets can have multiple different assembly parsers

llvm/include/llvm/Transforms/IPO/Attributor.h

if (isa<Instruction>(V))
       return cast<Instruction>(V).getFunction();
     return nullptr;
   }
 
   /// Return the associated argument, if any.
   Argument *getAssociatedArgument() const;
 
   /// Return true if the position refers to a function interface, that is the
-  /// function scope, the function return, or an argumnt.
+  /// function scope, the function return, or an argument.
   bool isFnInterfaceKind() const {
     switch (getPositionKind()) {
     case IRPosition::IRP_FUNCTION:
     case IRPosition::IRP_RETURNED:
     case IRPosition::IRP_ARGUMENT:
       return true;
     default:
       return false;

 /// - for IRP_CALL_SITE_RETURNED:
 ///   - the callee (IRP_RETURNED), if known
 ///   - the call site (IRP_FUNCTION)
 ///   - the callee (IRP_FUNCTION), if known
 /// - for IRP_CALL_SITE_ARGUMENT:
 ///   - the argument of the callee (IRP_ARGUMENT), if known
 ///   - the callee (IRP_FUNCTION), if known
 ///   - the position the call site argument is associated with if it is not
-///     anchored to the call site, e.g., if it is an arugment then the argument
+///     anchored to the call site, e.g., if it is an argument then the argument
 ///     (IRP_ARGUMENT)
 class SubsumingPositionIterator {
   SmallVector<IRPosition, 4> IRPositions;
   using iterator = decltype(IRPositions)::iterator;
 
 public:
   SubsumingPositionIterator(const IRPosition &IRP);
   iterator begin() { return IRPositions.begin(); }

 struct AAAlign : public IRAttribute<
                      Attribute::Alignment,
                      StateWrapper<AAAlignmentStateType, AbstractAttribute>> {
   AAAlign(const IRPosition &IRP) : IRAttribute(IRP) {}
 
   /// Return assumed alignment.
   unsigned getAssumedAlign() const { return getAssumed(); }
 
-  /// Return known alignemnt.
+  /// Return known alignment.
   unsigned getKnownAlign() const { return getKnown(); }
 
   /// Create an abstract attribute view for the position \p IRP.
   static AAAlign &createForPosition(const IRPosition &IRP, Attributor &A);
 
   /// Unique ID (due to the unique address)
   static const char ID;
 };

llvm/lib/Bitcode/Reader/MetadataLoader.cpp

if (auto *MDN = dyn_cast<MDNode>(MD))
       assert(MDN->isResolved() &&
              "Flushing Placeholder while cycles aren't resolved");
 #endif
     PHs.front().replaceUseWith(MD);
     PHs.pop_front();
   }
 }
 
-} // anonynous namespace
+} // anonymous namespace
 
 static Error error(const Twine &Message) {
   return make_error<StringError>(
       Message, make_error_code(BitcodeError::CorruptedBitcode));
 }
 
 class MetadataLoader::MetadataLoaderImpl {
   BitcodeReaderMetadataList MetadataList;

llvm/lib/CodeGen/Analysis.cpp

static bool isNoopBitcast(Type *T1, Type *T2,
   return T1 == T2 || (T1->isPointerTy() && T2->isPointerTy()) ||
          (isa<VectorType>(T1) && isa<VectorType>(T2) &&
           TLI.isTypeLegal(EVT::getEVT(T1)) && TLI.isTypeLegal(EVT::getEVT(T2)));
 }
 
 /// Look through operations that will be free to find the earliest source of
 /// this value.
 ///
-/// @param ValLoc If V has aggegate type, we will be interested in a particular
+/// @param ValLoc If V has aggregate type, we will be interested in a particular
 /// scalar component. This records its address; the reverse of this list gives a
 /// sequence of indices appropriate for an extractvalue to locate the important
 /// value. This value is updated during the function and on exit will indicate
 /// similar information for the Value returned.
 ///
 /// @param DataBits If this function looks through truncate instructions, this
 /// will record the smallest size attained.
 static const Value *getNoopInput(const Value *V,

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
   ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
   return Res;
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
   assert(NVT == ExtPassThru.getValueType() &&
-      "Gather result type and the passThru agrument type should be the same");
+      "Gather result type and the passThru argument type should be the same");
 
   SDLoc dl(N);
   SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
                    N->getIndex(), N->getScale() };
   SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
                                     N->getMemoryVT(), dl, Ops,
                                     N->getMemOperand(), N->getIndexType());
   // Legalize the chain result - switch anything that used the old chain to

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (STy || !Index.getValueType().isVector()) {
     Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
   }
   return true;
 }
 
 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
   SDLoc sdl = getCurSDLoc();
 
-  // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
+  // llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask)
   const Value *Ptr = I.getArgOperand(1);
   SDValue Src0 = getValue(I.getArgOperand(0));
   SDValue Mask = getValue(I.getArgOperand(3));
   EVT VT = Src0.getValueType();
   unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
   if (!Alignment)
     Alignment = DAG.getEVTAlignment(VT);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

tryInstructionTransform(MachineBasicBlock::iterator &mi,
   bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
 
   if (Register::isVirtualRegister(regA))
     scanUses(regA);
 
   bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
 
   // If the instruction is convertible to 3 Addr, instead
-  // of returning try 3 Addr transformation aggresively and
+  // of returning try 3 Addr transformation aggressively and
   // use this variable to check later. Because it might be better.
   // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
   // instead of the following code.
   //   addl     %esi, %edi
   //   movl     %edi, %eax
   //   ret
   if (Commuted && !MI.isConvertibleTo3Addr())
     return false;

llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp

 
 struct ContentDescriptor {
   dwarf::LineNumberEntryFormat Type;
   dwarf::Form Form;
 };
 
 using ContentDescriptors = SmallVector<ContentDescriptor, 4>;
 
-} // end anonmyous namespace
+} // end anonymous namespace
 
 void DWARFDebugLine::ContentTypeTracker::trackContentType(
     dwarf::LineNumberEntryFormat ContentType) {
   switch (ContentType) {
   case dwarf::DW_LNCT_timestamp:
     HasModTime = true;
     break;
   case dwarf::DW_LNCT_size:

llvm/lib/MC/MCAssembler.cpp

else
     encodeULEB128(Value, OSE, OldSize);
   return OldSize != LF.getContents().size();
 }
 
 /// Check if the branch crosses the boundary.
 ///
 /// \param StartAddr start address of the fused/unfused branch.
 /// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
 /// \returns true if the branch cross the boundary.
 static bool mayCrossBoundary(uint64_t StartAddr, uint64_t Size,
                              Align BoundaryAlignment) {
   uint64_t EndAddr = StartAddr + Size;
   return (StartAddr >> Log2(BoundaryAlignment)) !=
          ((EndAddr - 1) >> Log2(BoundaryAlignment));
 }
 
 /// Check if the branch is against the boundary.
 ///
 /// \param StartAddr start address of the fused/unfused branch.
 /// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
 /// \returns true if the branch is against the boundary.
 static bool isAgainstBoundary(uint64_t StartAddr, uint64_t Size,
                               Align BoundaryAlignment) {
   uint64_t EndAddr = StartAddr + Size;
   return (EndAddr & (BoundaryAlignment.value() - 1)) == 0;
 }
 
 /// Check if the branch needs padding.
 ///
 /// \param StartAddr start address of the fused/unfused branch.
 /// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
 /// \returns true if the branch needs padding.
 static bool needPadding(uint64_t StartAddr, uint64_t Size,
                         Align BoundaryAlignment) {
   return mayCrossBoundary(StartAddr, Size, BoundaryAlignment) ||
          isAgainstBoundary(StartAddr, Size, BoundaryAlignment);
 }
 
 bool MCAssembler::relaxBoundaryAlign(MCAsmLayout &Layout,

llvm/lib/MC/MCExpr.cpp

 ///
 /// This routine conceptually attempts to construct an MCValue:
 ///   Result = (Result_A - Result_B + Result_Cst)
 /// from two MCValue's LHS and RHS where
 ///   Result = LHS + RHS
 /// and
 ///   Result = (LHS_A - LHS_B + LHS_Cst) + (RHS_A - RHS_B + RHS_Cst).
 ///
-/// This routine attempts to aggresively fold the operands such that the result
+/// This routine attempts to aggressively fold the operands such that the result
 /// is representable in an MCValue, but may not always succeed.
 ///
 /// \returns True on success, false if the result is not representable in an
 /// MCValue.
 
 /// NOTE: It is really important to have both the Asm and Layout arguments.
 /// They might look redundant, but this function can be used before layout
 /// is done (see the object streamer for example) and having the Asm argument

llvm/lib/MC/MCParser/COFFAsmParser.cpp

class COFFAsmParser : public MCAsmParserExtension {
   bool ParseAtUnwindOrAtExcept(bool &unwind, bool &except);
   bool ParseSEHRegisterNumber(unsigned &RegNo);
   bool ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc);
 
 public:
   COFFAsmParser() = default;
 };
 
-} // end annonomous namespace.
+} // end anonymous namespace.
 
 static SectionKind computeSectionKind(unsigned Flags) {
   if (Flags & COFF::IMAGE_SCN_MEM_EXECUTE)
     return SectionKind::getText();
   if (Flags & COFF::IMAGE_SCN_MEM_READ &&
       (Flags & COFF::IMAGE_SCN_MEM_WRITE) == 0)
     return SectionKind::getReadOnly();
   return SectionKind::getData();

llvm/lib/ProfileData/GCOV.cpp

 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 /// dump - Dump GCOVBlock content to dbgs() for debugging purposes.
 LLVM_DUMP_METHOD void GCOVBlock::dump() const { print(dbgs()); }
 #endif
 
 //===----------------------------------------------------------------------===//
 // Cycles detection
 //
-// The algorithm in GCC is based on the algorihtm by Hawick & James:
+// The algorithm in GCC is based on the algorithm by Hawick & James:
 //   "Enumerating Circuits and Loops in Graphs with Self-Arcs and Multiple-Arcs"
 //   http://complexity.massey.ac.nz/cstn/013/cstn-013.pdf.
 
 /// Get the count for the detected cycle.
 uint64_t GCOVBlock::getCycleCount(const Edges &Path) {
   uint64_t CycleCount = std::numeric_limits<uint64_t>::max();
   for (auto E : Path) {
     CycleCount = std::min(E->CyclesCount, CycleCount);

llvm/lib/Target/AArch64/AArch64CallLowering.cpp

bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   // constraint of that instruction.
   if (Info.Callee.isReg())
     MIB->getOperand(0).setReg(constrainOperandRegClass(
         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
         0));
 
   // Finally we can copy the returned value back into its virtual-register. In
-  // symmetry with the arugments, the physical register must be an
+  // symmetry with the arguments, the physical register must be an
   // implicit-define of the call instruction.
   if (!Info.OrigRet.Ty->isVoidTy()) {
     CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
     if (!handleAssignments(MIRBuilder, InArgs, Handler))
       return false;
   }
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

def QQQ  : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
   let Size = 384;
 }
 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
   let Size = 512;
 }
 
 
 // Vector operand versions of the FP registers. Alternate name printing and
-// assmebler matching.
+// assembler matching.
 def VectorReg64AsmOperand : AsmOperandClass {
   let Name = "VectorReg64";
   let PredicateMethod = "isNeonVectorReg";
 }
 def VectorReg128AsmOperand : AsmOperandClass {
   let Name = "VectorReg128";
   let PredicateMethod = "isNeonVectorReg";
 }

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

-//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer  -------------------===//
+//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file

llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp

-//===-- R600AsmPrinter.cpp - R600 Assebly printer  ------------------------===//
+//===-- R600AsmPrinter.cpp - R600 Assembly printer ------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file

llvm/lib/Target/ARM/ARMCallingConv.cpp

static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
                                           CCState &State) {
   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
 
   // AAPCS HFAs must have 1-4 elements, all of the same type
   if (PendingMembers.size() > 0)
     assert(PendingMembers[0].getLocVT() == LocVT);
 
   // Add the argument to the list to be allocated once we know the size of the
-  // aggregate. Store the type's required alignmnent as extra info for later: in
+  // aggregate. Store the type's required alignment as extra info for later: in
   // the [N x i64] case all trace has been removed by the time we actually get
   // to do allocation.
   PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
                                                    ArgFlags.getOrigAlign()));
 
   if (!ArgFlags.isInConsecutiveRegsLast())
     return true;
 

llvm/lib/Target/ARM/ARMISelLowering.cpp

 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
                                                        unsigned Alignment,
                                                        MachineMemOperand::Flags,
                                                        bool *Fast) const {
   // Depends what it gets converted into if the type is weird.
   if (!VT.isSimple())
     return false;
 
-  // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
+  // The AllowsUnaligned flag models the SCTLR.A setting in ARM cpus
   bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
   auto Ty = VT.getSimpleVT().SimpleTy;
 
   if (Ty == MVT::i8 || Ty == MVT::i16 || Ty == MVT::i32) {
     // Unaligned access can use (for example) LRDB, LRDH, LDR
     if (AllowsUnaligned) {
       if (Fast)
         *Fast = Subtarget->hasV7Ops();

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 static void applyMnemonicAliases(StringRef &Mnemonic,
                                  const FeatureBitset &Features,
                                  unsigned VariantID);
 
 // The GNU assembler has aliases of ldrd and strd with the second register
 // omitted. We don't have a way to do that in tablegen, so fix it up here.
 //
 // We have to be careful to not emit an invalid Rt2 here, because the rest of
-// the assmebly parser could then generate confusing diagnostics refering to
+// the assembly parser could then generate confusing diagnostics refering to
 // it. If we do find anything that prevents us from doing the transformation we
 // bail out, and let the assembly parser report an error on the instruction as
 // it is written.
 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
                                      OperandVector &Operands) {
   if (Mnemonic != "ldrd" && Mnemonic != "strd")
     return;
   if (Operands.size() < 4)

llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h

 //===-- ARMUnwindOpAsm.h - ARM Unwind Opcodes Assembler ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the unwind opcode assmebler for ARM exception handling
+// This file declares the unwind opcode assembler for ARM exception handling
 // table.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
 
 #include "llvm/ADT/SmallVector.h"

llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp

 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the unwind opcode assmebler for ARM exception handling
+// This file implements the unwind opcode assembler for ARM exception handling
 // table.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMUnwindOpAsm.h"
 #include "llvm/Support/ARMEHABI.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/MathExtras.h"

llvm/lib/Target/Hexagon/HexagonRegisterInfo.td

let Namespace = "Hexagon" in {
   }
 
   // Predicate registers.
   def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
   def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
   def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
   def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
 
-  // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
+  // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc-
   // tions modify this bit, and multiple such instructions are allowed in the
   // same packet. We need to ignore output dependencies on this bit, but not
   // on the entire USR.
   def USR_OVF : Rc<?, "usr.ovf">;
 
   def USR  : Rc<8,  "usr",       ["c8"]>,   DwarfRegNum<[75]> {
     let SubRegIndices = [subreg_overflow];
     let SubRegs = [USR_OVF];

llvm/lib/Target/Mips/MipsInstrFPU.td

 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
     DecoderNamespace="MipsFP64" in {
   def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
   def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
 }
 
-/// Floating-point Aritmetic
+/// Floating-point Arithmetic
 let AdditionalPredicates = [NotInMicroMips] in {
   def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
                ADDS_FM<0x00, 16>, ISA_MIPS1;
   defm FADD :  ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>,
                ISA_MIPS1;
   def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
                ADDS_FM<0x03, 16>, ISA_MIPS1;
   defm FDIV :  ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (!MFI.isFixedObjectIndex(FrIdx)) {
       // need to use the XForm.
       if (offsetMinAlignForOpcode(Opcode) > 1)
         return true;
     }
 
     // This is eiher:
     // 1) A fixed frame index object which we know are aligned so
     // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
-    // need to consider the alignement here.
+    // need to consider the alignment here.
     // 2) A not fixed object but in that case we now know that the min required
     // alignment is no more than 1 based on the previous check.
     if (InstrInfo->isXFormMemOp(Opcode))
       return true;
   }
   return false;
 }
 

llvm/lib/Target/X86/X86InstrAVX512.td

def : Pat<(v8i64 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
             (!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
   }
 }
 
 defm : AVX512_pmovx_patterns<"VPMOVSX", sext, sext_invec>;
 defm : AVX512_pmovx_patterns<"VPMOVZX", zext, zext_invec>;
 
 // Without BWI we can't do a trunc from v16i16 to v16i8. DAG combine can merge
-// ext+trunc aggresively making it impossible to legalize the DAG to this
+// ext+trunc aggressively making it impossible to legalize the DAG to this
 // pattern directly.
 let Predicates = [HasAVX512, NoBWI] in {
 def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))),
          (VPMOVDBZrr (v16i32 (VPMOVZXWDZrr VR256X:$src)))>;
 def: Pat<(v16i8 (trunc (loadv16i16 addr:$src))),
          (VPMOVDBZrr (v16i32 (VPMOVZXWDZrm addr:$src)))>;
 }
 

llvm/lib/Transforms/IPO/Attributor.cpp

 
 static cl::opt<bool> DisableAttributor(
     "attributor-disable", cl::Hidden,
     cl::desc("Disable the attributor inter-procedural deduction pass."),
     cl::init(true));
 
 static cl::opt<bool> AnnotateDeclarationCallSites(
     "attributor-annotate-decl-cs", cl::Hidden,
-    cl::desc("Annoate call sites of function declarations."), cl::init(false));
+    cl::desc("Annotate call sites of function declarations."), cl::init(false));
 
 static cl::opt<bool> ManifestInternal(
     "attributor-manifest-internal", cl::Hidden,
     cl::desc("Manifest Attributor internal string attributes."),
     cl::init(false));
 
 static cl::opt<unsigned> DepRecInterval(
     "attributor-dependence-recompute-interval", cl::Hidden,
ChangeStatus manifest(Attributor &A) override {
 
     // Check for users that allow alignment annotations.
     Value &AnchorVal = getIRPosition().getAnchorValue();
     for (const Use &U : AnchorVal.uses()) {
       if (auto *SI = dyn_cast<StoreInst>(U.getUser())) {
         if (SI->getPointerOperand() == &AnchorVal)
           if (SI->getAlignment() < getAssumedAlign()) {
             STATS_DECLTRACK(AAAlign, Store,
-                            "Number of times alignemnt added to a store");
+                            "Number of times alignment added to a store");
             SI->setAlignment(Align(getAssumedAlign()));
             Changed = ChangeStatus::CHANGED;
           }
       } else if (auto *LI = dyn_cast<LoadInst>(U.getUser())) {
         if (LI->getPointerOperand() == &AnchorVal)
           if (LI->getAlignment() < getAssumedAlign()) {
             LI->setAlignment(Align(getAssumedAlign()));
             STATS_DECLTRACK(AAAlign, Load,
-                            "Number of times alignemnt added to a load");
+                            "Number of times alignment added to a load");
             Changed = ChangeStatus::CHANGED;
           }
       }
     }
 
     return AAAlign::manifest(A) | Changed;
   }
 

llvm/lib/Transforms/IPO/PartialInlining.cpp

while (OutliningInfo->GetNumInlinedBlocks() < MaxNumInlineBlocks) {
     OutliningInfo->NonReturnBlock = NonReturnBlock;
     OutliningInfo->ReturnBlockPreds.push_back(Cand);
     Entries.insert(Cand);
   }
 
   return OutliningInfo;
 }
 
-// Check if there is PGO data or user annoated branch data:
+// Check if there is PGO data or user annotated branch data:
 static bool hasProfileData(Function *F, FunctionOutliningInfo *OI) {
   if (F->hasProfileData())
     return true;
   // Now check if any of the entry block has MD_prof data:
   for (auto *E : OI->Entries) {
     BranchInst *BR = dyn_cast<BranchInst>(E->getTerminator());
     if (!BR || BR->isUnconditional())
       continue;

llvm/lib/Transforms/Utils/AddDiscriminators.cpp

static bool addDiscriminators(Function &F) {
   // Traverse all instructions and assign new discriminators to call
   // instructions with the same lineno that are in the same basic block.
   // Sample base profile needs to distinguish different function calls within
   // a same source line for correct profile annotation.
   for (BasicBlock &B : F) {
     LocationSet CallLocations;
     for (auto &I : B.getInstList()) {
       // We bypass intrinsic calls for the following two reasons:
-      //  1) We want to avoid a non-deterministic assigment of
+      //  1) We want to avoid a non-deterministic assignment of
       //     discriminators.
       //  2) We want to minimize the number of base discriminators used.
       if (!isa<InvokeInst>(I) && (!isa<CallInst>(I) || isa<IntrinsicInst>(I)))  
         continue;
 
       DILocation *CurrentDIL = I.getDebugLoc();
       if (!CurrentDIL)
         continue;

llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll

 ; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt -enable-misched=false < %s | FileCheck %s
-; Check that lowered argumens do not overwrite the return address before it is moved.
+; Check that lowered arguments do not overwrite the return address before it is moved.
 ; Bug 6225
 ;
 ; If a call is a fastcc tail call and tail call optimization is enabled, the
 ; caller frame is replaced by the callee frame. This can require that arguments are
 ; placed on the former return address stack slot. Special care needs to be taken
 ; taken that the return address is moved / or stored in a register before
 ; lowering of arguments potentially overwrites the value.
 ;

llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-linux-gnu  | FileCheck %s
 
 declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0);
 
 ; In RegCall calling convention, ESI and EDI are callee saved registers.
 ; One might think that the caller could assume that ESI value is the same before
 ; and after calling the callee.
 ; However, RegCall also says that a register that was used for
-; passing/returning argumnets, can be assumed to be modified by the callee.
+; passing/returning arguments, can be assumed to be modified by the callee.
 ; In other words, it is no longer a callee saved register.
 ; In this case we want to see that EDX/ECX values are saved and EDI/ESI are assumed
 ; to be modified by the callee.
 ; This is a hipe CC function that doesn't save any register for the caller.
 ; So we can be sure that there is no other reason to save EDX/ECX.
 ; The caller arguments are expected to be passed (in the following order)
 ; in registers: ESI, EBP, EAX, EDX and ECX.
 define cc 11 i32 @caller(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {

llvm/test/CodeGen/X86/lea.ll

 ; WIN-NEXT:    retq
   %tmp1 = shl i32 %x, 3
   %tmp2 = add i32 %tmp1, 7
   ret i32 %tmp2
 }
 
 
 ; ISel the add of -4 with a neg and use an lea for the rest of the
-; arithemtic.
+; arithmetic.
 define i32 @test2(i32 %x_offs) nounwind readnone {
 ; LINUX-LABEL: test2:
 ; LINUX:       # %bb.0: # %entry
 ; LINUX-NEXT:    # kill: def $edi killed $edi def $rdi
 ; LINUX-NEXT:    cmpl $5, %edi
 ; LINUX-NEXT:    jl .LBB1_2
 ; LINUX-NEXT:  # %bb.1: # %bb.nph
 ; LINUX-NEXT:    leal -5(%rdi), %eax

llvm/test/CodeGen/X86/masked_gather_scatter.ll

; SKX_32-NEXT:    retl
   %gt2 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
   %res = add <16 x i32> %gt1, %gt2
   ret <16 x i32> %res
 }
 
 %struct.RT = type { i8, [10 x [20 x i32]], i8 }
 %struct.ST = type { i32, double, %struct.RT }
 
-; Masked gather for agregate types
+; Masked gather for aggregate types
 ; Test9 and Test10 should give the same result (scalar and vector indices in GEP)
 
 
 define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
 ; KNL_64-LABEL: test9:
 ; KNL_64:       # %bb.0: # %entry
 ; KNL_64-NEXT:    vpbroadcastq %rdi, %zmm2
 ; KNL_64-NEXT:    vpbroadcastq {{.*#+}} zmm3 = [824,824,824,824,824,824,824,824]

llvm/test/CodeGen/X86/swifterror.ll

 ; CHECK-APPLE: nop
 ; CHECK-APPLE: popq  %r12
 define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
   call void asm sideeffect "nop", "~{r12}"()
   ret void
 }
 
 ; CHECK-APPLE-LABEL: params_in_reg
-; Save callee save registers to store clobbered arugments.
+; Save callee save registers to store clobbered arguments.
 ; CHECK-APPLE:  pushq   %rbp
 ; CHECK-APPLE:  pushq   %r15
 ; CHECK-APPLE:  pushq   %r14
 ; Clobbered swiftself register.
 ; CHECK-APPLE:  pushq   %r13
 ; CHECK-APPLE:  pushq   %rbx
 ; CHECK-APPLE:  subq    $48, %rsp
 ; Save arguments.

llvm/test/LTO/X86/parallel.ll

 ; RUN: llvm-as -o %t.bc %s
 ; RUN: llvm-lto -exported-symbol=foo -exported-symbol=bar -j2 -o %t.o %t.bc
 ; RUN: llvm-nm %t.o.0 | FileCheck --check-prefix=CHECK0 %s
 ; RUN: llvm-nm %t.o.1 | FileCheck --check-prefix=CHECK1 %s
 
-; FIXME: Investigate test failures on these architecures.
+; FIXME: Investigate test failures on these architectures.
 ; UNSUPPORTED: mips, mipsel, aarch64, powerpc64
 
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK0-NOT: bar
 ; CHECK0: T foo
 ; CHECK0-NOT: bar
 define void @foo() {

llvm/test/MC/AArch64/arm64-directive_loh.s

 .loh AdrpAdrp L1, L2, L3
 
 # Too much arguments with alternative syntax.
 # CHECK-ERRORS: error: unexpected token in '.loh' directive
 # CHECK-ERRORS-NEXT: .loh 1 L1, L2, L3
 # CHECK-ERRORS-NEXT:              ^
 .loh 1 L1, L2, L3
 
-# Too few argumets.
+# Too few arguments.
 # CHECK-ERRORS: error: unexpected token in '.loh' directive
 # CHECK-ERRORS-NEXT: .loh AdrpAdrp L1
 # CHECK-ERRORS-NEXT:                 ^
 .loh AdrpAdrp L1
 
-# Too few argumets with alternative syntax.
+# Too few arguments with alternative syntax.
 # CHECK-ERRORS: error: unexpected token in '.loh' directive
 # CHECK-ERRORS-NEXT: .loh 1 L1
 # CHECK-ERRORS-NEXT:          ^
 .loh 1 L1

llvm/test/MC/ARM/misaligned-blx.s

 @ RUN: not llvm-mc -triple thumbv7-apple-ios -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s
         @ Size: 2 bytes
         .thumb_func _f1
         .thumb
         .globl _f1
 _f1:
         bx lr
 
-        @ A misalgined ARM destination.
+        @ A misaligned ARM destination.
         .arm
         .globl _misaligned
 _misaligned:
         bx lr
 
         @ And a properly aligned one.
         .globl _aligned
         .p2align 2

llvm/test/Transforms/DeadArgElim/naked_functions.ll

 ; RUN: opt -S -deadargelim %s | FileCheck %s
 
-; Don't eliminate dead arugments from naked functions.
+; Don't eliminate dead arguments from naked functions.
 ; CHECK: define internal i32 @naked(i32 %x)
 
 define internal i32 @naked(i32 %x) #0 {
   tail call void asm sideeffect inteldialect "mov eax, [esp + $$4]\0A\09ret", "~{eax},~{dirflag},~{fpsr},~{flags}"()
   unreachable
 }
 
 

llvm/test/Transforms/SCCP/apint-basictest3.ll

 ; This is a basic sanity check for constant propagation.  It tests the basic
-; arithmatic operations.
+; arithmetic operations.
 
 
 ; RUN: opt < %s -sccp -S | not grep mul
 ; RUN: opt < %s -sccp -S | not grep umod
 
 define i128 @test(i1 %B) {
   br i1 %B, label %BB1, label %BB2
 BB1:

llvm/test/Transforms/SLPVectorizer/X86/align.ll

entry:
   %arrayidx4 = getelementptr inbounds double, double* %b, i64 1
   %i4 = load double, double* %arrayidx4, align 8
   %mul5 = fmul double %i3, %i4
   store double %mul, double* %store1
   store double %mul5, double* %store2, align 16
   ret void
 }
 
-; Float has 4 byte abi alignment on x86_64. We must use the alignmnet of the
+; Float has 4 byte abi alignment on x86_64. We must use the alignment of the
 ; value being loaded/stored not the alignment of the pointer type.
 
 define void @test2(float * %a, float * %b) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A1:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 1
 ; CHECK-NEXT:    [[A2:%.*]] = getelementptr inbounds float, float* [[A]], i64 2
 ; CHECK-NEXT:    [[A3:%.*]] = getelementptr inbounds float, float* [[A]], i64 3

llvm/tools/llvm-c-test/echo.cpp

 #include <stdlib.h>
 
 using namespace llvm;
 
 // Provide DenseMapInfo for C API opaque types.
 template<typename T>
 struct CAPIDenseMap {};
 
-// The default DenseMapInfo require to know about pointer alignement.
-// Because the C API uses opaques pointer types, their alignement is unknown.
+// The default DenseMapInfo require to know about pointer alignment.
+// Because the C API uses opaques pointer types, their alignment is unknown.
 // As a result, we need to roll out our own implementation.
 template<typename T>
 struct CAPIDenseMap<T*> {
   struct CAPIDenseMapInfo {
     static inline T* getEmptyKey() {
       uintptr_t Val = static_cast<uintptr_t>(-1);
       return reinterpret_cast<T*>(Val);
     }

llvm/tools/llvm-objdump/MachODump.cpp

if (!symbolTableWorked) {
                 << "invalid instruction encoding\n";
             if (InstSize == 0)
               InstSize = 1; // skip illegible bytes
           }
         }
       }
     }
     // The TripleName's need to be reset if we are called again for a different
-    // archtecture.
+    // architecture.
     TripleName = "";
     ThumbTripleName = "";
 
     if (SymbolizerInfo.demangled_name != nullptr)
       free(SymbolizerInfo.demangled_name);
     if (ThumbSymbolizerInfo.demangled_name != nullptr)
       free(ThumbSymbolizerInfo.demangled_name);
   }

llvm/unittests/Analysis/VectorFunctionABITest.cpp

TEST_F(VFABIParserTest, InvalidParameter) {
   EXPECT_FALSE(invokeParser("_ZGVsM2vX_sin"));
 }
 
 TEST_F(VFABIParserTest, Align) {
   EXPECT_TRUE(invokeParser("_ZGVsN2l2a2_sin"));
   EXPECT_EQ(Parameters.size(), (unsigned)1);
   EXPECT_EQ(Parameters[0].Alignment, Align(2));
 
-  // Missing alignement value.
+  // Missing alignment value.
   EXPECT_FALSE(invokeParser("_ZGVsM2l2a_sin"));
   // Invalid alignment token "x".
   EXPECT_FALSE(invokeParser("_ZGVsM2l2ax_sin"));
   // Alignment MUST be associated to a paramater.
   EXPECT_FALSE(invokeParser("_ZGVsM2a2_sin"));
   // Alignment must be a power of 2.
   EXPECT_FALSE(invokeParser("_ZGVsN2l2a0_sin"));
   EXPECT_TRUE(invokeParser("_ZGVsN2l2a1_sin"));

llvm/unittests/Analysis/VectorUtilsTest.cpp

#define __BUILD_PARAMETERS(Kind)                                               \
   EXPECT_TRUE(validParams(__BUILD_PARAMETERS(VFParamKind::OMP_LinearRefPos)));
   EXPECT_TRUE(validParams(__BUILD_PARAMETERS(VFParamKind::OMP_LinearValPos)));
   EXPECT_TRUE(validParams(__BUILD_PARAMETERS(VFParamKind::OMP_LinearUValPos)));
 #undef __BUILD_PARAMETERS
 }
 
 TEST_F(VFShapeAPITest, Parameters_Invalid) {
 #ifndef NDEBUG
-  // Wrong order is checked by an asseretion: make sure that the
+  // Wrong order is checked by an assertion: make sure that the
   // assertion is not removed.
   EXPECT_DEATH(validParams({{1, VFParamKind::Vector}}),
                "Broken parameter list.");
   EXPECT_DEATH(
       validParams({{1, VFParamKind::Vector}, {0, VFParamKind::Vector}}),
       "Broken parameter list.");
 #endif
 

llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp

-//=== WebAssemblyExceptionInfoTest.cpp - WebAssebmlyExceptionInfo unit tests =//
+//=== WebAssemblyExceptionInfoTest.cpp - WebAssemblyExceptionInfo unit tests =//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyExceptionInfo.h"

llvm/utils/TableGen/CodeGenTarget.h

public:
   /// this target.
   ///
   bool getAllowRegisterRenaming() const;
 
   /// getAsmParser - Return the AssemblyParser definition for this target.
   ///
   Record *getAsmParser() const;
 
-  /// getAsmParserVariant - Return the AssmblyParserVariant definition for
+  /// getAsmParserVariant - Return the AssemblyParserVariant definition for
   /// this target.
   ///
   Record *getAsmParserVariant(unsigned i) const;
 
-  /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
+  /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
   /// available for this target.
   ///
   unsigned getAsmParserVariantCount() const;
 
   /// getAsmWriter - Return the AssemblyWriter definition for this target.
   ///
   Record *getAsmWriter() const;
 

llvm/utils/TableGen/CodeGenTarget.cpp

 Record *CodeGenTarget::getAsmParser() const {
   std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
   if (AsmParserNum >= LI.size())
     PrintFatalError("Target does not have an AsmParser #" +
                     Twine(AsmParserNum) + "!");
   return LI[AsmParserNum];
 }
 
-/// getAsmParserVariant - Return the AssmblyParserVariant definition for
+/// getAsmParserVariant - Return the AssemblyParserVariant definition for
 /// this target.
 ///
 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
   std::vector<Record*> LI =
     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
   if (i >= LI.size())
     PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
                     "!");
   return LI[i];
 }
 
-/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
+/// getAsmParserVariantCount - Return the AssemblyParserVariant definition
 /// available for this target.
 ///
 unsigned CodeGenTarget::getAsmParserVariantCount() const {
   std::vector<Record*> LI =
     TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
   return LI.size();
 }
 

llvm/utils/bugpoint/RemoteRunSafely.sh

 }
 
 moreArgsExpected()
 {
   # $1 - remaining number of arguments
   # $2 - number of arguments to shift
   if [ $1 -lt $2 ]
   then
-    echo "Error: Wrong number of argumants."
+    echo "Error: Wrong number of arguments."
     printUsageAndExit
   fi
 }
 
 # Save a copy of the original arguments in a string before we
 # clobber them with the shift command.
 ORIG_ARGS="$*"
 #DEBUG: echo 'GOT: '$ORIG_ARGS