After bugfix the undef value case here, we used more operations to implement inserting vxi1 sub vector into vXi1 vector, I optimize it by use less operations.
The history information at https://reviews.llvm.org/D68311
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[X86] Optimization of inserting vxi1 sub vector into vXi1 vector ClosedPublic Authored by xiangzhangllvm on Dec 26 2019, 6:03 PM.
Details Summary After bugfix the undef value case here, we used more operations to implement inserting vxi1 sub vector into vXi1 vector, I optimize it by use less operations. The history information at https://reviews.llvm.org/D68311
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xiangzhangllvm added inline comments.
Comment Actions update the patch, and I tested in my local performance test, it really have a little small improvement. lebedev.ri retitled this revision from Optimization of inserting vxi1 sub vector into vXi1 vector to [X86] Optimization of inserting vxi1 sub vector into vXi1 vector .Jan 2 2020, 12:15 AM This revision is now accepted and ready to land.Jan 2 2020, 11:34 AM Closed by commit rG9dc9e0ea64f5: [X86] Optimization of inserting vxi1 sub vector into vXi1 vector (authored by Wang, Pengfei <pengfei.wang@intel.com>). · Explain WhyJan 2 2020, 5:28 PM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 235979 llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx512-calling-conv.ll
llvm/test/CodeGen/X86/avx512-ext.ll
llvm/test/CodeGen/X86/avx512-insert-extract.ll
llvm/test/CodeGen/X86/avx512-mask-op.ll
llvm/test/CodeGen/X86/masked_store.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
llvm/test/CodeGen/X86/vec_smulo.ll
llvm/test/CodeGen/X86/vec_umulo.ll
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APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems) ?