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Differential D63839

[ARM] Widening loads and narrowing stores
ClosedPublic

Authored by dmgreen on Jun 26 2019, 1:22 PM.

Details

Reviewers
t.p.northover
simon_tatham
SjoerdMeijer
samparker
ostannard
Commits
rGeb7080ac6e5e: [ARM] Widening loads and narrowing stores
rL364636: [ARM] Widening loads and narrowing stores
Summary

MVE has instructions to widen as it loads, and narrow as it stores. This adds the required patterns and legalisation to make them work.

Patch by David Sherwood.

Diff Detail

Repository
rL LLVM

Event Timeline

dmgreen created this revision.Jun 26 2019, 1:22 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 26 2019, 1:23 PM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
dmgreen added a child revision: D63840: [ARM] Add support for MVE pre and post inc loads and stores..Jun 26 2019, 1:37 PM
dmgreen added a parent revision: D63838: [ARM] MVE loads and stores.
samparker accepted this revision.Jun 26 2019, 11:27 PM

LGTM

This revision is now accepted and ready to land.Jun 26 2019, 11:27 PM
Closed by commit rL364636: [ARM] Widening loads and narrowing stores (authored by dmgreen). · Explain WhyJun 28 2019, 2:49 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
1 line
25 lines
36 lines
test/
CodeGen/
Thumb2/
437 lines
420 lines
414 lines
25 lines
127 lines

Diff 207018

llvm/trunk/lib/Target/ARM/ARMISelLowering.h

Show First 20 Lines • Show All 808 Lines • ▼ Show 20 Lines private:
MachineBasicBlock *EmitStructByval(MachineInstr &MI, MachineBasicBlock *EmitStructByval(MachineInstr &MI,
MachineBasicBlock *MBB) const; MachineBasicBlock *MBB) const;
MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
MachineBasicBlock *MBB) const; MachineBasicBlock *MBB) const;
MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
MachineBasicBlock *MBB) const; MachineBasicBlock *MBB) const;
void addMVEVectorTypes(bool HasMVEFP); void addMVEVectorTypes(bool HasMVEFP);
void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
void setAllExpand(MVT VT); void setAllExpand(MVT VT);
}; };
enum NEONModImmType { enum NEONModImmType {
VMOVModImm, VMOVModImm,
VMVNModImm, VMVNModImm,
OtherModImm OtherModImm
}; };
Show All 11 Lines

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Linesvoid ARMTargetLowering::addQRTypeForNEON(MVT VT) {
addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
} }
void ARMTargetLowering::setAllExpand(MVT VT) { void ARMTargetLowering::setAllExpand(MVT VT) {
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
setOperationAction(Opc, VT, Expand); setOperationAction(Opc, VT, Expand);
} }
void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
LegalizeAction Action) {
setLoadExtAction(ISD::EXTLOAD, From, To, Action);
setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
}
void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) { void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 }; const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
for (auto VT : IntTypes) { for (auto VT : IntTypes) {
addRegisterClass(VT, &ARM::QPRRegClass); addRegisterClass(VT, &ARM::QPRRegClass);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
Show All 35 Linesvoid ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 }; const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
for (auto VT : LongTypes) { for (auto VT : LongTypes) {
addRegisterClass(VT, &ARM::QPRRegClass); addRegisterClass(VT, &ARM::QPRRegClass);
setAllExpand(VT); setAllExpand(VT);
setOperationAction(ISD::BITCAST, VT, Legal); setOperationAction(ISD::BITCAST, VT, Legal);
setOperationAction(ISD::LOAD, VT, Legal); setOperationAction(ISD::LOAD, VT, Legal);
setOperationAction(ISD::STORE, VT, Legal); setOperationAction(ISD::STORE, VT, Legal);
} }
// It is legal to extload from v4i8 to v4i16 or v4i32.
addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
// Some truncating stores are legal too.
setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
} }
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
const ARMSubtarget &STI) const ARMSubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) { : TargetLowering(TM), Subtarget(&STI) {
RegInfo = Subtarget->getRegisterInfo(); RegInfo = Subtarget->getRegisterInfo();
Itins = Subtarget->getInstrItineraryData(); Itins = Subtarget->getInstrItineraryData();
▲ Show 20 Lines • Show All 294 Lines • ▼ Show 20 Lines if (Subtarget->hasFullFP16()) {
setOperationAction(ISD::FMINNUM, MVT::f16, Legal); setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
} }
for (MVT VT : MVT::vector_valuetypes()) { for (MVT VT : MVT::vector_valuetypes()) {
for (MVT InnerVT : MVT::vector_valuetypes()) { for (MVT InnerVT : MVT::vector_valuetypes()) {
setTruncStoreAction(VT, InnerVT, Expand); setTruncStoreAction(VT, InnerVT, Expand);
setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); addAllExtLoads(VT, InnerVT, Expand);
setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
} }
setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::MULHS, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand);
setOperationAction(ISD::MULHU, VT, Expand); setOperationAction(ISD::MULHU, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand);
setOperationAction(ISD::BSWAP, VT, Expand); setOperationAction(ISD::BSWAP, VT, Expand);
▲ Show 20 Lines • Show All 12,591 Lines • ▼ Show 20 Lines if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
return true; return true;
} }
} }
if (!Subtarget->hasMVEIntegerOps()) if (!Subtarget->hasMVEIntegerOps())
return false; return false;
if (Ty != MVT::v16i8 && Ty != MVT::v8i16 && Ty != MVT::v8f16 && if (Ty != MVT::v16i8 && Ty != MVT::v8i16 && Ty != MVT::v8f16 &&
Ty != MVT::v4i32 && Ty != MVT::v4f32 && Ty != MVT::v2i64 && Ty != MVT::v4i32 && Ty != MVT::v4f32 && Ty != MVT::v2i64 &&
Ty != MVT::v2f64) Ty != MVT::v2f64 &&
// These are for truncated stores
Ty != MVT::v4i8 && Ty != MVT::v8i8 && Ty != MVT::v4i16)
return false; return false;
if (Subtarget->isLittle()) { if (Subtarget->isLittle()) {
// In little-endian MVE, the store instructions VSTRB.U8, // In little-endian MVE, the store instructions VSTRB.U8,
// VSTRH.U16 and VSTRW.U32 all store the vector register in // VSTRH.U16 and VSTRW.U32 all store the vector register in
// exactly the same format, and differ only in the range of // exactly the same format, and differ only in the range of
// their immediate offset field and the required alignment. // their immediate offset field and the required alignment.
// //
▲ Show 20 Lines • Show All 2,386 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 4,195 Lines • ▼ Show 20 Lineslet Predicates = [HasMVEInt, IsBE] in {
def : MVE_unpred_vector_load_typed<v16i8, MVE_VLDRBU8, load, 0>; def : MVE_unpred_vector_load_typed<v16i8, MVE_VLDRBU8, load, 0>;
def : MVE_unpred_vector_load_typed<v8i16, MVE_VLDRHU16, alignedload16, 1>; def : MVE_unpred_vector_load_typed<v8i16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_unpred_vector_load_typed<v8f16, MVE_VLDRHU16, alignedload16, 1>; def : MVE_unpred_vector_load_typed<v8f16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_unpred_vector_load_typed<v4i32, MVE_VLDRWU32, alignedload32, 2>; def : MVE_unpred_vector_load_typed<v4i32, MVE_VLDRWU32, alignedload32, 2>;
def : MVE_unpred_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>; def : MVE_unpred_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>;
} }
// Widening/Narrowing Loads/Stores
let Predicates = [HasMVEInt] in {
def : Pat<(truncstorevi8 (v8i16 MQPR:$val), t2addrmode_imm7<1>:$addr),
(MVE_VSTRB16 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
def : Pat<(truncstorevi8 (v4i32 MQPR:$val), t2addrmode_imm7<1>:$addr),
(MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
def : Pat<(truncstorevi16 (v4i32 MQPR:$val), t2addrmode_imm7<2>:$addr),
(MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<2>:$addr)>;
}
multiclass MVEExtLoad<string DestLanes, string DestElemBits,
string SrcElemBits, string SrcElemType,
Operand am> {
def _Any : Pat<(!cast<ValueType>("v" # DestLanes # "i" # DestElemBits)
(!cast<PatFrag>("extloadvi" # SrcElemBits) am:$addr)),
(!cast<Instruction>("MVE_VLDR" # SrcElemType # "U" # DestElemBits)
am:$addr)>;
def _Z : Pat<(!cast<ValueType>("v" # DestLanes # "i" # DestElemBits)
(!cast<PatFrag>("zextloadvi" # SrcElemBits) am:$addr)),
(!cast<Instruction>("MVE_VLDR" # SrcElemType # "U" # DestElemBits)
am:$addr)>;
def _S : Pat<(!cast<ValueType>("v" # DestLanes # "i" # DestElemBits)
(!cast<PatFrag>("sextloadvi" # SrcElemBits) am:$addr)),
(!cast<Instruction>("MVE_VLDR" # SrcElemType # "S" # DestElemBits)
am:$addr)>;
}
let Predicates = [HasMVEInt] in {
defm : MVEExtLoad<"4", "32", "8", "B", t2addrmode_imm7<1>>;
defm : MVEExtLoad<"8", "16", "8", "B", t2addrmode_imm7<1>>;
defm : MVEExtLoad<"4", "32", "16", "H", t2addrmode_imm7<2>>;
}
// Bit convert patterns // Bit convert patterns
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-ldst-offset.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhu32_4(i8* %x, i8* %y) { define i8* @post_ldrhu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_4: ; CHECK-LABEL: post_ldrhu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #4] ; CHECK-NEXT: vldrh.u32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #8]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #10]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhu32_3(i8* %x, i8* %y) { define i8* @post_ldrhu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_3: ; CHECK-LABEL: post_ldrhu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh.w r2, [r0, #3] ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r2]
; CHECK-NEXT: ldrh.w r2, [r0, #5]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh.w r2, [r0, #7]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh.w r2, [r0, #9]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhu32_2(i8* %x, i8* %y) { define i8* @post_ldrhu32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_2: ; CHECK-LABEL: post_ldrhu32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #2] ; CHECK-NEXT: adds r2, r0, #2
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r2]
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #8]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhu32_254(i8* %x, i8* %y) { define i8* @post_ldrhu32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_254: ; CHECK-LABEL: post_ldrhu32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh.w r2, [r0, #254] ; CHECK-NEXT: add.w r2, r0, #254
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r2]
; CHECK-NEXT: ldrh.w r2, [r0, #256]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh.w r2, [r0, #258]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh.w r2, [r0, #260]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhu32_256(i8* %x, i8* %y) { define i8* @post_ldrhu32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_256: ; CHECK-LABEL: post_ldrhu32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh.w r2, [r0, #256] ; CHECK-NEXT: add.w r2, r0, #256
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r2]
; CHECK-NEXT: ldrh.w r2, [r0, #258]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh.w r2, [r0, #260]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh.w r2, [r0, #262]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhs32_4(i8* %x, i8* %y) { define i8* @post_ldrhs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_4: ; CHECK-LABEL: post_ldrhs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r0, #4]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrsh.w r2, [r0, #4]
; CHECK-NEXT: ldrsh.w r3, [r0, #6]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #8]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #10]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhs32_3(i8* %x, i8* %y) { define i8* @post_ldrhs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_3: ; CHECK-LABEL: post_ldrhs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r2]
; CHECK-NEXT: ldrsh.w r2, [r0, #3]
; CHECK-NEXT: ldrsh.w r3, [r0, #5]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #7]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #9]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhs32_2(i8* %x, i8* %y) { define i8* @post_ldrhs32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_2: ; CHECK-LABEL: post_ldrhs32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r2, r0, #2
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r2]
; CHECK-NEXT: ldrsh.w r2, [r0, #2]
; CHECK-NEXT: ldrsh.w r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #8]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhs32_254(i8* %x, i8* %y) { define i8* @post_ldrhs32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_254: ; CHECK-LABEL: post_ldrhs32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #254
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r2]
; CHECK-NEXT: ldrsh.w r2, [r0, #254]
; CHECK-NEXT: ldrsh.w r3, [r0, #256]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #258]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #260]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrhs32_256(i8* %x, i8* %y) { define i8* @post_ldrhs32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_256: ; CHECK-LABEL: post_ldrhs32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #256
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r2]
; CHECK-NEXT: ldrsh.w r2, [r0, #256]
; CHECK-NEXT: ldrsh.w r3, [r0, #258]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #260]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #262]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu32_4(i8* %x, i8* %y) { define i8* @post_ldrbu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_4: ; CHECK-LABEL: post_ldrbu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0, #4]
; CHECK-NEXT: ldrb r3, [r0, #5]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #7]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu32_3(i8* %x, i8* %y) { define i8* @post_ldrbu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_3: ; CHECK-LABEL: post_ldrbu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r2]
; CHECK-NEXT: ldrb r2, [r0, #3]
; CHECK-NEXT: ldrb r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #5]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu32_127(i8* %x, i8* %y) { define i8* @post_ldrbu32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_127: ; CHECK-LABEL: post_ldrbu32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #127
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r2]
; CHECK-NEXT: ldrb.w r2, [r0, #127]
; CHECK-NEXT: ldrb.w r3, [r0, #128]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #129]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #130]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu32_128(i8* %x, i8* %y) { define i8* @post_ldrbu32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_128: ; CHECK-LABEL: post_ldrbu32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #128
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r2]
; CHECK-NEXT: ldrb.w r2, [r0, #128]
; CHECK-NEXT: ldrb.w r3, [r0, #129]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #130]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #131]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs32_4(i8* %x, i8* %y) { define i8* @post_ldrbs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_4: ; CHECK-LABEL: post_ldrbs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #4] ; CHECK-NEXT: vldrb.s32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs32_3(i8* %x, i8* %y) { define i8* @post_ldrbs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_3: ; CHECK-LABEL: post_ldrbs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #3] ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs32_127(i8* %x, i8* %y) { define i8* @post_ldrbs32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_127: ; CHECK-LABEL: post_ldrbs32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #127] ; CHECK-NEXT: add.w r2, r0, #127
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #128]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #129]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #130]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs32_128(i8* %x, i8* %y) { define i8* @post_ldrbs32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_128: ; CHECK-LABEL: post_ldrbs32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #128] ; CHECK-NEXT: add.w r2, r0, #128
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #129]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #130]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #131]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu16_4(i8* %x, i8* %y) { define i8* @post_ldrbu16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_4: ; CHECK-LABEL: post_ldrbu16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0, #4]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0, #4]
; CHECK-NEXT: ldrb r3, [r0, #5]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #6]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #7]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb r2, [r0, #8]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb r2, [r0, #9]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #10]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #11]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu16_3(i8* %x, i8* %y) { define i8* @post_ldrbu16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_3: ; CHECK-LABEL: post_ldrbu16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r2]
; CHECK-NEXT: ldrb r2, [r0, #3]
; CHECK-NEXT: ldrb r3, [r0, #4]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #5]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #6]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb r2, [r0, #8]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #9]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #10]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu16_127(i8* %x, i8* %y) { define i8* @post_ldrbu16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_127: ; CHECK-LABEL: post_ldrbu16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #127
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r2]
; CHECK-NEXT: ldrb.w r2, [r0, #127]
; CHECK-NEXT: ldrb.w r3, [r0, #128]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #129]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #130]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb.w r2, [r0, #131]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb.w r2, [r0, #132]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb.w r2, [r0, #133]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb.w r2, [r0, #134]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbu16_128(i8* %x, i8* %y) { define i8* @post_ldrbu16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_128: ; CHECK-LABEL: post_ldrbu16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: add.w r2, r0, #128
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r2]
; CHECK-NEXT: ldrb.w r2, [r0, #128]
; CHECK-NEXT: ldrb.w r3, [r0, #129]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #130]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #131]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb.w r2, [r0, #132]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb.w r2, [r0, #133]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb.w r2, [r0, #134]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb.w r2, [r0, #135]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs16_4(i8* %x, i8* %y) { define i8* @post_ldrbs16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_4: ; CHECK-LABEL: post_ldrbs16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #4] ; CHECK-NEXT: vldrb.s16 q0, [r0, #4]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #8]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #9]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #10]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #11]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs16_3(i8* %x, i8* %y) { define i8* @post_ldrbs16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_3: ; CHECK-LABEL: post_ldrbs16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #3] ; CHECK-NEXT: adds r2, r0, #3
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #8]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #9]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #10]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs16_127(i8* %x, i8* %y) { define i8* @post_ldrbs16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_127: ; CHECK-LABEL: post_ldrbs16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #127] ; CHECK-NEXT: add.w r2, r0, #127
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #128]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #129]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #130]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #131]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #132]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #133]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #134]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %x ret i8* %x
} }
define i8* @post_ldrbs16_128(i8* %x, i8* %y) { define i8* @post_ldrbs16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_128: ; CHECK-LABEL: post_ldrbs16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0, #128] ; CHECK-NEXT: add.w r2, r0, #128
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r2]
; CHECK-NEXT: ldrsb.w r2, [r0, #129]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #130]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #131]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #132]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #133]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #134]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #135]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strh32_4(i8* %y, i8* %x) { define i8* @post_strh32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_4: ; CHECK-LABEL: post_strh32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0, #4] ; CHECK-NEXT: vstrh.32 q0, [r0, #4]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strh32_3(i8* %y, i8* %x) { define i8* @post_strh32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_3: ; CHECK-LABEL: post_strh32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #3] ; CHECK-NEXT: adds r1, r0, #3
; CHECK-NEXT: str.w r2, [r0, #7] ; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strh32_2(i8* %y, i8* %x) { define i8* @post_strh32_2(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_2: ; CHECK-LABEL: post_strh32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #2] ; CHECK-NEXT: adds r1, r0, #2
; CHECK-NEXT: str.w r2, [r0, #6] ; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 2 %z = getelementptr inbounds i8, i8* %y, i32 2
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strh32_254(i8* %y, i8* %x) { define i8* @post_strh32_254(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_254: ; CHECK-LABEL: post_strh32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #254] ; CHECK-NEXT: add.w r1, r0, #254
; CHECK-NEXT: str.w r2, [r0, #258] ; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 254 %z = getelementptr inbounds i8, i8* %y, i32 254
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strh32_256(i8* %y, i8* %x) { define i8* @post_strh32_256(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_256: ; CHECK-LABEL: post_strh32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0, #256] ; CHECK-NEXT: add.w r1, r0, #256
; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 256 %z = getelementptr inbounds i8, i8* %y, i32 256
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %y ret i8* %y
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb32_4(i8* %y, i8* %x) { define i8* @post_strb32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_4: ; CHECK-LABEL: post_strb32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0, #4] ; CHECK-NEXT: vstrb.32 q0, [r0, #4]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb32_3(i8* %y, i8* %x) { define i8* @post_strb32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_3: ; CHECK-LABEL: post_strb32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #3] ; CHECK-NEXT: adds r1, r0, #3
; CHECK-NEXT: vstrb.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb32_127(i8* %y, i8* %x) { define i8* @post_strb32_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_127: ; CHECK-LABEL: post_strb32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #127] ; CHECK-NEXT: add.w r1, r0, #127
; CHECK-NEXT: vstrb.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb32_128(i8* %y, i8* %x) { define i8* @post_strb32_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_128: ; CHECK-LABEL: post_strb32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #128] ; CHECK-NEXT: add.w r1, r0, #128
; CHECK-NEXT: vstrb.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb16_4(i8* %y, i8* %x) { define i8* @post_strb16_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_4: ; CHECK-LABEL: post_strb16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0, #4] ; CHECK-NEXT: vstrb.16 q0, [r0, #4]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb16_3(i8* %y, i8* %x) { define i8* @post_strb16_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_3: ; CHECK-LABEL: post_strb16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #3] ; CHECK-NEXT: adds r1, r0, #3
; CHECK-NEXT: str.w r2, [r0, #7] ; CHECK-NEXT: vstrb.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb16_127(i8* %y, i8* %x) { define i8* @post_strb16_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_127: ; CHECK-LABEL: post_strb16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str.w r1, [r0, #127] ; CHECK-NEXT: add.w r1, r0, #127
; CHECK-NEXT: str.w r2, [r0, #131] ; CHECK-NEXT: vstrb.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %y ret i8* %y
} }
define i8* @post_strb16_128(i8* %y, i8* %x) { define i8* @post_strb16_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_128: ; CHECK-LABEL: post_strb16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0, #128] ; CHECK-NEXT: add.w r1, r0, #128
; CHECK-NEXT: vstrb.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %y ret i8* %y
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-ldst-postinc.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_4(i8* %x, i8* %y) { define i8* @post_ldrhu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_4: ; CHECK-LABEL: post_ldrhu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: ldrh r3, [r2, #4]!
; CHECK-NEXT: ldrh r0, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_3(i8* %x, i8* %y) { define i8* @post_ldrhu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_3: ; CHECK-LABEL: post_ldrhu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: adds r0, #3 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_2(i8* %x, i8* %y) { define i8* @post_ldrhu32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_2: ; CHECK-LABEL: post_ldrhu32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: ldrh r3, [r2, #2]!
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrh r3, [r0, #4]
; CHECK-NEXT: ldrh r0, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_254(i8* %x, i8* %y) { define i8* @post_ldrhu32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_254: ; CHECK-LABEL: post_ldrhu32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: adds r0, #254 ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_256(i8* %x, i8* %y) { define i8* @post_ldrhu32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_256: ; CHECK-LABEL: post_ldrhu32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_4(i8* %x, i8* %y) { define i8* @post_ldrhs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_4: ; CHECK-LABEL: post_ldrhs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh.w r2, [r0] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: ldrsh.w r3, [r0, #2] ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: ldrsh r2, [r0, #4]!
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_3(i8* %x, i8* %y) { define i8* @post_ldrhs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_3: ; CHECK-LABEL: post_ldrhs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrsh.w r2, [r0]
; CHECK-NEXT: ldrsh.w r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: adds r0, #3 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_2(i8* %x, i8* %y) { define i8* @post_ldrhs32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_2: ; CHECK-LABEL: post_ldrhs32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh.w r2, [r0] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: ldrsh.w r3, [r0, #4] ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh r2, [r0, #2]!
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_254(i8* %x, i8* %y) { define i8* @post_ldrhs32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_254: ; CHECK-LABEL: post_ldrhs32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrsh.w r2, [r0]
; CHECK-NEXT: ldrsh.w r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: adds r0, #254 ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_256(i8* %x, i8* %y) { define i8* @post_ldrhs32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_256: ; CHECK-LABEL: post_ldrhs32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrsh.w r2, [r0]
; CHECK-NEXT: ldrsh.w r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_4(i8* %x, i8* %y) { define i8* @post_ldrbu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_4: ; CHECK-LABEL: post_ldrbu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: adds r0, #4 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_3(i8* %x, i8* %y) { define i8* @post_ldrbu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_3: ; CHECK-LABEL: post_ldrbu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0] ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1] ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb r2, [r0, #3]!
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_127(i8* %x, i8* %y) { define i8* @post_ldrbu32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_127: ; CHECK-LABEL: post_ldrbu32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: adds r0, #127 ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_128(i8* %x, i8* %y) { define i8* @post_ldrbu32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_128: ; CHECK-LABEL: post_ldrbu32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_4(i8* %x, i8* %y) { define i8* @post_ldrbs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_4: ; CHECK-LABEL: post_ldrbs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: adds r0, #4 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_3(i8* %x, i8* %y) { define i8* @post_ldrbs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_3: ; CHECK-LABEL: post_ldrbs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb r2, [r0, #3]!
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_127(i8* %x, i8* %y) { define i8* @post_ldrbs32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_127: ; CHECK-LABEL: post_ldrbs32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: adds r0, #127 ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_128(i8* %x, i8* %y) { define i8* @post_ldrbs32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_128: ; CHECK-LABEL: post_ldrbs32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_4(i8* %x, i8* %y) { define i8* @post_ldrbu16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_4: ; CHECK-LABEL: post_ldrbu16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb r3, [r2, #4]!
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r3
; CHECK-NEXT: ldrb r3, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: ldrb r3, [r0, #6]
; CHECK-NEXT: ldrb r0, [r0, #7]
; CHECK-NEXT: vmov.16 q0[6], r3
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_3(i8* %x, i8* %y) { define i8* @post_ldrbu16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_3: ; CHECK-LABEL: post_ldrbu16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb r3, [r2, #3]!
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb.w lr, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], r3
; CHECK-NEXT: ldrb r3, [r0, #5]
; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: ldrb r3, [r0, #6]
; CHECK-NEXT: ldrb r0, [r0, #7]
; CHECK-NEXT: vmov.16 q0[6], r3
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_127(i8* %x, i8* %y) { define i8* @post_ldrbu16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_127: ; CHECK-LABEL: post_ldrbu16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: adds r0, #127 ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_128(i8* %x, i8* %y) { define i8* @post_ldrbu16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_128: ; CHECK-LABEL: post_ldrbu16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r3
; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r12
; CHECK-NEXT: ldrb r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], lr
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_4(i8* %x, i8* %y) { define i8* @post_ldrbs16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_4: ; CHECK-LABEL: post_ldrbs16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: ldrsb r3, [r2, #4]!
; CHECK-NEXT: vmov.16 q0[4], r3
; CHECK-NEXT: ldrsb.w r3, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: ldrsb.w r3, [r0, #6]
; CHECK-NEXT: ldrsb.w r0, [r0, #7]
; CHECK-NEXT: vmov.16 q0[6], r3
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_3(i8* %x, i8* %y) { define i8* @post_ldrbs16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_3: ; CHECK-LABEL: post_ldrbs16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: ldrsb r3, [r2, #3]!
; CHECK-NEXT: vmov.16 q0[3], r3
; CHECK-NEXT: ldrsb.w r3, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r3
; CHECK-NEXT: ldrsb.w r3, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: ldrsb.w r3, [r0, #6]
; CHECK-NEXT: ldrsb.w r0, [r0, #7]
; CHECK-NEXT: vmov.16 q0[6], r3
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_127(i8* %x, i8* %y) { define i8* @post_ldrbs16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_127: ; CHECK-LABEL: post_ldrbs16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: adds r0, #127 ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_128(i8* %x, i8* %y) { define i8* @post_ldrbs16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_128: ; CHECK-LABEL: post_ldrbs16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb.w r2, [r0] ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_4(i8* %y, i8* %x) { define i8* @post_strh32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_4: ; CHECK-LABEL: post_strh32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: str r2, [r0, #4]! ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_3(i8* %y, i8* %x) { define i8* @post_strh32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_3: ; CHECK-LABEL: post_strh32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: adds r0, #3 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_2(i8* %y, i8* %x) { define i8* @post_strh32_2(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_2: ; CHECK-LABEL: post_strh32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: adds r0, #2 ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 2 %z = getelementptr inbounds i8, i8* %y, i32 2
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_254(i8* %y, i8* %x) { define i8* @post_strh32_254(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_254: ; CHECK-LABEL: post_strh32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: adds r0, #254 ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 254 %z = getelementptr inbounds i8, i8* %y, i32 254
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_256(i8* %y, i8* %x) { define i8* @post_strh32_256(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_256: ; CHECK-LABEL: post_strh32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 256 %z = getelementptr inbounds i8, i8* %y, i32 256
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_4(i8* %y, i8* %x) { define i8* @post_strb32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_4: ; CHECK-LABEL: post_strb32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0], #4 ; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %y to <4 x i8>* %2 = bitcast i8* %y to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_3(i8* %y, i8* %x) { define i8* @post_strb32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_3: ; CHECK-LABEL: post_strb32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0], #3 ; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %y to <4 x i8>* %2 = bitcast i8* %y to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_127(i8* %y, i8* %x) { define i8* @post_strb32_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_127: ; CHECK-LABEL: post_strb32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0], #127 ; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %y to <4 x i8>* %2 = bitcast i8* %y to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_128(i8* %y, i8* %x) { define i8* @post_strb32_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_128: ; CHECK-LABEL: post_strb32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0], #128 ; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %y to <4 x i8>* %2 = bitcast i8* %y to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_4(i8* %y, i8* %x) { define i8* @post_strb16_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_4: ; CHECK-LABEL: post_strb16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str r1, [r0] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: str r2, [r0, #4]! ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %y to <8 x i8>* %2 = bitcast i8* %y to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_3(i8* %y, i8* %x) { define i8* @post_strb16_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_3: ; CHECK-LABEL: post_strb16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: adds r0, #3 ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %y to <8 x i8>* %2 = bitcast i8* %y to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_127(i8* %y, i8* %x) { define i8* @post_strb16_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_127: ; CHECK-LABEL: post_strb16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: adds r0, #127 ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %y to <8 x i8>* %2 = bitcast i8* %y to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_128(i8* %y, i8* %x) { define i8* @post_strb16_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_128: ; CHECK-LABEL: post_strb16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: strd r1, r2, [r0] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %y to <8 x i8>* %2 = bitcast i8* %y to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-ldst-preinc.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_4(i8* %x, i8* %y) { define i8* @post_ldrhu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_4: ; CHECK-LABEL: post_ldrhu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #4]! ; CHECK-NEXT: vldrh.u32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_3(i8* %x, i8* %y) { define i8* @post_ldrhu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_3: ; CHECK-LABEL: post_ldrhu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #3]! ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_2(i8* %x, i8* %y) { define i8* @post_ldrhu32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_2: ; CHECK-LABEL: post_ldrhu32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #2]! ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_254(i8* %x, i8* %y) { define i8* @post_ldrhu32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_254: ; CHECK-LABEL: post_ldrhu32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r2, [r0, #254]! ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: ldrh r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh r2, [r0, #4]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh r2, [r0, #6]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhu32_256(i8* %x, i8* %y) { define i8* @post_ldrhu32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhu32_256: ; CHECK-LABEL: post_ldrhu32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh.w r2, [r0, #256]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrh.w r2, [r0, #258]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrh.w r2, [r0, #260]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrh.w r2, [r0, #262]
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: vmov.32 q0[3], r2 ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = zext <4 x i16> %1 to <4 x i32> %2 = zext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_4(i8* %x, i8* %y) { define i8* @post_ldrhs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_4: ; CHECK-LABEL: post_ldrhs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh r2, [r0, #4]! ; CHECK-NEXT: vldrh.s32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrsh.w r2, [r0, #2]
; CHECK-NEXT: ldrsh.w r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_3(i8* %x, i8* %y) { define i8* @post_ldrhs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_3: ; CHECK-LABEL: post_ldrhs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh r2, [r0, #3]! ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: ldrsh.w r2, [r0, #2]
; CHECK-NEXT: ldrsh.w r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_2(i8* %x, i8* %y) { define i8* @post_ldrhs32_2(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_2: ; CHECK-LABEL: post_ldrhs32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh r2, [r0, #2]! ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: ldrsh.w r2, [r0, #2]
; CHECK-NEXT: ldrsh.w r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 2 %z = getelementptr inbounds i8, i8* %x, i32 2
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_254(i8* %x, i8* %y) { define i8* @post_ldrhs32_254(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_254: ; CHECK-LABEL: post_ldrhs32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsh r2, [r0, #254]! ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: ldrsh.w r2, [r0, #2]
; CHECK-NEXT: ldrsh.w r3, [r0, #4]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #6]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 254 %z = getelementptr inbounds i8, i8* %x, i32 254
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrhs32_256(i8* %x, i8* %y) { define i8* @post_ldrhs32_256(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrhs32_256: ; CHECK-LABEL: post_ldrhs32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrsh.w r2, [r0, #256]
; CHECK-NEXT: ldrsh.w r3, [r0, #258]
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrsh.w r12, [r0, #260]
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: ldrsh.w lr, [r0, #262]
; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: vmov.32 q0[3], lr ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 256 %z = getelementptr inbounds i8, i8* %x, i32 256
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = sext <4 x i16> %1 to <4 x i32> %2 = sext <4 x i16> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_4(i8* %x, i8* %y) { define i8* @post_ldrbu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_4: ; CHECK-LABEL: post_ldrbu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0, #4]! ; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_3(i8* %x, i8* %y) { define i8* @post_ldrbu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_3: ; CHECK-LABEL: post_ldrbu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0, #3]! ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_127(i8* %x, i8* %y) { define i8* @post_ldrbu32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_127: ; CHECK-LABEL: post_ldrbu32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0, #127]! ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu32_128(i8* %x, i8* %y) { define i8* @post_ldrbu32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu32_128: ; CHECK-LABEL: post_ldrbu32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0, #128]! ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_4(i8* %x, i8* %y) { define i8* @post_ldrbs32_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_4: ; CHECK-LABEL: post_ldrbs32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #4]! ; CHECK-NEXT: vldrb.s32 q0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_3(i8* %x, i8* %y) { define i8* @post_ldrbs32_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_3: ; CHECK-LABEL: post_ldrbs32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #3]! ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_127(i8* %x, i8* %y) { define i8* @post_ldrbs32_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_127: ; CHECK-LABEL: post_ldrbs32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #127]! ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs32_128(i8* %x, i8* %y) { define i8* @post_ldrbs32_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs32_128: ; CHECK-LABEL: post_ldrbs32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #128]! ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vldrb.s32 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.32 q0[3], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <4 x i8>* %0 = bitcast i8* %z to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = sext <4 x i8> %1 to <4 x i32> %2 = sext <4 x i8> %1 to <4 x i32>
%3 = bitcast i8* %y to <4 x i32>* %3 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %2, <4 x i32>* %3, align 8 store <4 x i32> %2, <4 x i32>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_4(i8* %x, i8* %y) { define i8* @post_ldrbu16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_4: ; CHECK-LABEL: post_ldrbu16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0, #4]
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrb r2, [r0, #4]!
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r3
; CHECK-NEXT: ldrb.w lr, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], r12
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_3(i8* %x, i8* %y) { define i8* @post_ldrbu16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_3: ; CHECK-LABEL: post_ldrbu16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #3]!
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r3
; CHECK-NEXT: ldrb.w lr, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], r12
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_127(i8* %x, i8* %y) { define i8* @post_ldrbu16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_127: ; CHECK-LABEL: post_ldrbu16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #127]!
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r3
; CHECK-NEXT: ldrb.w lr, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], r12
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbu16_128(i8* %x, i8* %y) { define i8* @post_ldrbu16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbu16_128: ; CHECK-LABEL: post_ldrbu16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: ldrb r2, [r0, #128]!
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb r2, [r0, #1]
; CHECK-NEXT: ldrb r3, [r0, #2]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrb.w r12, [r0, #3]
; CHECK-NEXT: vmov.16 q0[2], r3
; CHECK-NEXT: ldrb.w lr, [r0, #4]
; CHECK-NEXT: vmov.16 q0[3], r12
; CHECK-NEXT: ldrb r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrb r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrb r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = zext <8 x i8> %1 to <8 x i16> %2 = zext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_4(i8* %x, i8* %y) { define i8* @post_ldrbs16_4(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_4: ; CHECK-LABEL: post_ldrbs16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #4]! ; CHECK-NEXT: vldrb.s16 q0, [r0, #4]
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_3(i8* %x, i8* %y) { define i8* @post_ldrbs16_3(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_3: ; CHECK-LABEL: post_ldrbs16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #3]! ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_127(i8* %x, i8* %y) { define i8* @post_ldrbs16_127(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_127: ; CHECK-LABEL: post_ldrbs16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #127]! ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 127 %z = getelementptr inbounds i8, i8* %x, i32 127
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %2, <8 x i16>* %3, align 8 store <8 x i16> %2, <8 x i16>* %3, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_ldrbs16_128(i8* %x, i8* %y) { define i8* @post_ldrbs16_128(i8* %x, i8* %y) {
; CHECK-LABEL: post_ldrbs16_128: ; CHECK-LABEL: post_ldrbs16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrsb r2, [r0, #128]! ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vldrb.s16 q0, [r0]
; CHECK-NEXT: ldrsb.w r2, [r0, #1]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #2]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #5]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #6]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: ldrsb.w r2, [r0, #7]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 128 %z = getelementptr inbounds i8, i8* %x, i32 128
%0 = bitcast i8* %z to <8 x i8>* %0 = bitcast i8* %z to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = sext <8 x i8> %1 to <8 x i16> %2 = sext <8 x i8> %1 to <8 x i16>
%3 = bitcast i8* %y to <8 x i16>* %3 = bitcast i8* %y to <8 x i16>*
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %1, <4 x i32>* %2, align 8 store <4 x i32> %1, <4 x i32>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_4(i8* %y, i8* %x) { define i8* @post_strh32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_4: ; CHECK-LABEL: post_strh32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0, #4]! ; CHECK-NEXT: vstrh.32 q0, [r0, #4]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_3(i8* %y, i8* %x) { define i8* @post_strh32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_3: ; CHECK-LABEL: post_strh32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: str r1, [r0, #3]! ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_2(i8* %y, i8* %x) { define i8* @post_strh32_2(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_2: ; CHECK-LABEL: post_strh32_2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: str r1, [r0, #2]! ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 2 %z = getelementptr inbounds i8, i8* %y, i32 2
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_254(i8* %y, i8* %x) { define i8* @post_strh32_254(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_254: ; CHECK-LABEL: post_strh32_254:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #254
; CHECK-NEXT: str r1, [r0, #254]! ; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 254 %z = getelementptr inbounds i8, i8* %y, i32 254
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strh32_256(i8* %y, i8* %x) { define i8* @post_strh32_256(i8* %y, i8* %x) {
; CHECK-LABEL: post_strh32_256: ; CHECK-LABEL: post_strh32_256:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1]
; CHECK-NEXT: strd r1, r2, [r0, #256]
; CHECK-NEXT: add.w r0, r0, #256 ; CHECK-NEXT: add.w r0, r0, #256
; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 256 %z = getelementptr inbounds i8, i8* %y, i32 256
%0 = bitcast i8* %x to <4 x i16>* %0 = bitcast i8* %x to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 8 %1 = load <4 x i16>, <4 x i16>* %0, align 8
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 8 store <4 x i16> %1, <4 x i16>* %2, align 8
ret i8* %z ret i8* %z
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
store <8 x i16> %1, <8 x i16>* %2, align 8 store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_4(i8* %y, i8* %x) { define i8* @post_strb32_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_4: ; CHECK-LABEL: post_strb32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: str r1, [r0, #4]! ; CHECK-NEXT: vstrb.32 q0, [r0, #4]
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_3(i8* %y, i8* %x) { define i8* @post_strb32_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_3: ; CHECK-LABEL: post_strb32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: str r1, [r0, #3]! ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_127(i8* %y, i8* %x) { define i8* @post_strb32_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_127: ; CHECK-LABEL: post_strb32_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: str r1, [r0, #127]! ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb32_128(i8* %y, i8* %x) { define i8* @post_strb32_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb32_128: ; CHECK-LABEL: post_strb32_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r1, [r1] ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: str r1, [r0, #128]! ; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <4 x i8>* %0 = bitcast i8* %x to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 8 %1 = load <4 x i8>, <4 x i8>* %0, align 8
%2 = bitcast i8* %z to <4 x i8>* %2 = bitcast i8* %z to <4 x i8>*
store <4 x i8> %1, <4 x i8>* %2, align 8 store <4 x i8> %1, <4 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_4(i8* %y, i8* %x) { define i8* @post_strb16_4(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_4: ; CHECK-LABEL: post_strb16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str r1, [r0, #4]! ; CHECK-NEXT: vstrb.16 q0, [r0, #4]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_3(i8* %y, i8* %x) { define i8* @post_strb16_3(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_3: ; CHECK-LABEL: post_strb16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: str r1, [r0, #3]! ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_127(i8* %y, i8* %x) { define i8* @post_strb16_127(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_127: ; CHECK-LABEL: post_strb16_127:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #127
; CHECK-NEXT: str r1, [r0, #127]! ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 127 %z = getelementptr inbounds i8, i8* %y, i32 127
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
} }
define i8* @post_strb16_128(i8* %y, i8* %x) { define i8* @post_strb16_128(i8* %y, i8* %x) {
; CHECK-LABEL: post_strb16_128: ; CHECK-LABEL: post_strb16_128:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r1, r2, [r1] ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: str r1, [r0, #128]! ; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: str r2, [r0, #4] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 128 %z = getelementptr inbounds i8, i8* %y, i32 128
%0 = bitcast i8* %x to <8 x i8>* %0 = bitcast i8* %x to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = bitcast i8* %z to <8 x i8>* %2 = bitcast i8* %z to <8 x i8>*
store <8 x i8> %1, <8 x i8>* %2, align 8 store <8 x i8> %1, <8 x i8>* %2, align 8
ret i8* %z ret i8* %z
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-shuffle.ll

Show First 20 Lines • Show All 488 Lines • ▼ Show 20 Linesentry:
ret <8 x half> %res ret <8 x half> %res
} }
define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) { define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
; CHECK-LABEL: scalar_to_vector_i32: ; CHECK-LABEL: scalar_to_vector_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #8 ; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: movs r0, #7 ; CHECK-NEXT: adr r1, .LCPI30_0
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: strh.w r0, [sp, #2]
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: strh.w r0, [sp] ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: movt r1, #9 ; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: ldr r0, [sp] ; CHECK-NEXT: mov r2, sp
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: bx lr ; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vstrh.32 q0, [r2]
; CHECK-NEXT: ldrd r0, r1, [sp], #8
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI30_0:
; CHECK-NEXT: .zero 4
; CHECK-NEXT: .long 7 @ 0x7
; CHECK-NEXT: .long 1 @ 0x1
; CHECK-NEXT: .long 9 @ 0x9
entry: entry:
%f = shufflevector <8 x i16> %v, <8 x i16> <i16 undef, i16 7, i16 1, i16 9, i16 undef, i16 undef, i16 undef, i16 undef>, <4 x i32> <i32 0, i32 9, i32 10, i32 11> %f = shufflevector <8 x i16> %v, <8 x i16> <i16 undef, i16 7, i16 1, i16 9, i16 undef, i16 undef, i16 undef, i16 undef>, <4 x i32> <i32 0, i32 9, i32 10, i32 11>
%0 = bitcast <4 x i16> %f to i64 %0 = bitcast <4 x i16> %f to i64
ret i64 %0 ret i64 %0
} }
define arm_aapcs_vfpcc i32 @extract_i32_0(<4 x i32> %a) { define arm_aapcs_vfpcc i32 @extract_i32_0(<4 x i32> %a) {
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-widen-narrow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s
define void @foo_int8_int32(<4 x i8>* %dest, <4 x i32>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int8_int32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i32>, <4 x i32>* %src, align 4
%0 = trunc <4 x i32> %wide.load to <4 x i8>
store <4 x i8> %0, <4 x i8>* %dest, align 1
ret void
}
define void @foo_int16_int32(<4 x i16>* %dest, <4 x i32>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int16_int32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrh.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i32>, <4 x i32>* %src, align 4
%0 = trunc <4 x i32> %wide.load to <4 x i16>
store <4 x i16> %0, <4 x i16>* %dest, align 2
ret void
}
define void @foo_int8_int16(<8 x i8>* %dest, <8 x i16>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int8_int16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <8 x i16>, <8 x i16>* %src, align 2
%0 = trunc <8 x i16> %wide.load to <8 x i8>
store <8 x i8> %0, <8 x i8>* %dest, align 1
ret void
}
define void @foo_int32_int8(<4 x i32>* %dest, <4 x i8>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int32_int8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.s32 q0, [r1]
; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i8>, <4 x i8>* %src, align 1
%0 = sext <4 x i8> %wide.load to <4 x i32>
store <4 x i32> %0, <4 x i32>* %dest, align 4
ret void
}
define void @foo_int16_int8(<8 x i16>* %dest, <8 x i8>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int16_int8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.s16 q0, [r1]
; CHECK-NEXT: vstrh.16 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <8 x i8>, <8 x i8>* %src, align 1
%0 = sext <8 x i8> %wide.load to <8 x i16>
store <8 x i16> %0, <8 x i16>* %dest, align 2
ret void
}
define void @foo_int32_int16(<4 x i32>* %dest, <4 x i16>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_int32_int16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r1]
; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i16>, <4 x i16>* %src, align 2
%0 = sext <4 x i16> %wide.load to <4 x i32>
store <4 x i32> %0, <4 x i32>* %dest, align 4
ret void
}
define void @foo_uint32_uint8(<4 x i32>* %dest, <4 x i8>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_uint32_uint8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u32 q0, [r1]
; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i8>, <4 x i8>* %src, align 1
%0 = zext <4 x i8> %wide.load to <4 x i32>
store <4 x i32> %0, <4 x i32>* %dest, align 4
ret void
}
define void @foo_uint16_uint8(<8 x i16>* %dest, <8 x i8>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_uint16_uint8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u16 q0, [r1]
; CHECK-NEXT: vstrh.16 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <8 x i8>, <8 x i8>* %src, align 1
%0 = zext <8 x i8> %wide.load to <8 x i16>
store <8 x i16> %0, <8 x i16>* %dest, align 2
ret void
}
define void @foo_uint32_uint16(<4 x i32>* %dest, <4 x i16>* readonly %src, i32 %n) {
; CHECK-LABEL: foo_uint32_uint16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u32 q0, [r1]
; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%wide.load = load <4 x i16>, <4 x i16>* %src, align 2
%0 = zext <4 x i16> %wide.load to <4 x i32>
store <4 x i32> %0, <4 x i32>* %dest, align 4
ret void
}