[ARM] MVE integer min and max

[dmgreen]

Summary

This makes the MVE integer min and max instructions legal and adds the relevant patterns for them.

[samparker]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
   const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
 
   for (auto VT : IntTypes) {
     addRegisterClass(VT, &ARM::QPRRegClass);
     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+    setOperationAction(ISD::SMIN, VT, Legal);
+    setOperationAction(ISD::SMAX, VT, Legal);
+    setOperationAction(ISD::UMIN, VT, Legal);
+    setOperationAction(ISD::UMAX, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);
     setOperationAction(ISD::SDIV, VT, Expand);
     setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SREM, VT, Expand);
 
     if (!HasMVEFP) {

llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

multiclass MVE_VMINMAX_all_sizes<string iname, bit bit_4> {
   def u8  : MVE_VMINMAX<iname, "u8",  0b1, 0b00, bit_4>;
   def u16 : MVE_VMINMAX<iname, "u16", 0b1, 0b01, bit_4>;
   def u32 : MVE_VMINMAX<iname, "u32", 0b1, 0b10, bit_4>;
 }
 
 defm MVE_VMAX : MVE_VMINMAX_all_sizes<"vmax", 0b0>;
 defm MVE_VMIN : MVE_VMINMAX_all_sizes<"vmin", 0b1>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v16i8 (smin (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VMINs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (smin (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VMINs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (smin (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VMINs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+  def : Pat<(v16i8 (smax (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VMAXs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (smax (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VMAXs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (smax (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VMAXs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+  def : Pat<(v16i8 (umin (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VMINu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (umin (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VMINu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (umin (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VMINu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+  def : Pat<(v16i8 (umax (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VMAXu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (umax (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VMAXu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (umax (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VMAXu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+}
+
 // end of mve_comp instructions
 
 // start of mve_imm_shift instructions
 
 def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
                       (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
                       NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
                       vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {

llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
 
+define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: smin_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.s8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <16 x i8> %s1, %s2
+  %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @smin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: smin_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.s16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <8 x i16> %s1, %s2
+  %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @smin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: smin_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.s32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <4 x i32> %s1, %s2
+  %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: umin_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.u8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ult <16 x i8> %s1, %s2
+  %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @umin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: umin_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.u16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ult <8 x i16> %s1, %s2
+  %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @umin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: umin_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.u32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ult <4 x i32> %s1, %s2
+  %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+  ret <4 x i32> %1
+}
+
+
+define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: smax_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.s8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp sgt <16 x i8> %s1, %s2
+  %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @smax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: smax_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.s16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp sgt <8 x i16> %s1, %s2
+  %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @smax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: smax_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.s32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp sgt <4 x i32> %s1, %s2
+  %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: umax_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.u8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ugt <16 x i8> %s1, %s2
+  %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @umax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: umax_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.u16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ugt <8 x i16> %s1, %s2
+  %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @umax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: umax_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.u32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp ugt <4 x i32> %s1, %s2
+  %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+  ret <4 x i32> %1
+}
+
+
 define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {
 ; CHECK-MVE-LABEL: maxnm_float32_t:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vmaxnm.f32 s11, s7, s3
 ; CHECK-MVE-NEXT:    vmaxnm.f32 s10, s6, s2
 ; CHECK-MVE-NEXT:    vmaxnm.f32 s9, s5, s1
 ; CHECK-MVE-NEXT:    vmaxnm.f32 s8, s4, s0
 ; CHECK-MVE-NEXT:    vmov q0, q2