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[ARM] Mark math routines as non-legal for MVE
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Authored by dmgreen on Jun 24 2019, 9:42 AM.

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Details

Reviewers

t.p.northover
simon_tatham
samparker
SjoerdMeijer
ostannard

Commits

rG28839440352d: [ARM] Mark math routines as non-legal for MVE
rL364641: [ARM] Mark math routines as non-legal for MVE

Summary

This adds handling and tests for a number of floating point math routines.

Diff Detail

Repository: rL LLVM

Event Timeline

dmgreen created this revision.Jun 24 2019, 9:42 AM

Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2019, 9:43 AM

Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript

looks very reasonable to me.

This revision is now accepted and ready to land.Jun 24 2019, 1:28 PM

dmgreen added a parent revision: D63595: [ARM] Mark div and rem as expand for MVE.Jun 25 2019, 5:00 AM

dmgreen added a child revision: D63861: [ARM] MVE patterns for abs and neg..Jun 27 2019, 2:49 AM

Closed by commit rL364641: [ARM] Mark math routines as non-legal for MVE (authored by dmgreen). · Explain WhyJun 28 2019, 4:18 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

ARM/

ARMISelLowering.cpp

9 lines

test/

CodeGen/

Thumb2/

mve-fmath.ll

2322 lines

Diff 207032

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Lines	for (auto VT : FloatTypes) {
setOperationAction(ISD::BITCAST, VT, Legal);		setOperationAction(ISD::BITCAST, VT, Legal);
setOperationAction(ISD::LOAD, VT, Legal);		setOperationAction(ISD::LOAD, VT, Legal);
setOperationAction(ISD::STORE, VT, Legal);		setOperationAction(ISD::STORE, VT, Legal);

if (HasMVEFP) {		if (HasMVEFP) {
// No native support for these.		// No native support for these.
setOperationAction(ISD::FDIV, VT, Expand);		setOperationAction(ISD::FDIV, VT, Expand);
setOperationAction(ISD::FREM, VT, Expand);		setOperationAction(ISD::FREM, VT, Expand);
		setOperationAction(ISD::FSQRT, VT, Expand);
		setOperationAction(ISD::FSIN, VT, Expand);
		setOperationAction(ISD::FCOS, VT, Expand);
		setOperationAction(ISD::FPOW, VT, Expand);
		setOperationAction(ISD::FLOG, VT, Expand);
		setOperationAction(ISD::FLOG2, VT, Expand);
		setOperationAction(ISD::FLOG10, VT, Expand);
		setOperationAction(ISD::FEXP, VT, Expand);
		setOperationAction(ISD::FEXP2, VT, Expand);
}		}
}		}

// We 'support' these types up to bitcast/load/store level, regardless of		// We 'support' these types up to bitcast/load/store level, regardless of
// MVE integer-only / float support. Only doing FP data processing on the FP		// MVE integer-only / float support. Only doing FP data processing on the FP
// vector types is inhibited at integer-only level.		// vector types is inhibited at integer-only level.
const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };		const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
for (auto VT : LongTypes) {		for (auto VT : LongTypes) {
▲ Show 20 Lines • Show All 15,331 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll

				; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
				; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
				; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - \| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP

				define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: sqrt_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: vsqrt.f32 s4, s0
				; CHECK-MVE-NEXT: movs r0, #0
				; CHECK-MVE-NEXT: vsqrt.f32 s6, s1
				; CHECK-MVE-NEXT: vsqrt.f32 s8, s2
				; CHECK-MVE-NEXT: vsqrt.f32 s10, s3
				; CHECK-MVE-NEXT: vdup.32 q0, r0
				; CHECK-MVE-NEXT: vmov.f32 s0, s4
				; CHECK-MVE-NEXT: vmov.f32 s1, s6
				; CHECK-MVE-NEXT: vmov.f32 s2, s8
				; CHECK-MVE-NEXT: vmov.f32 s3, s10
				; CHECK-MVE-NEXT: bx lr
				;
				; CHECK-MVEFP-LABEL: sqrt_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: vsqrt.f32 s4, s0
				; CHECK-MVEFP-NEXT: vsqrt.f32 s5, s1
				; CHECK-MVEFP-NEXT: vsqrt.f32 s6, s2
				; CHECK-MVEFP-NEXT: vsqrt.f32 s7, s3
				; CHECK-MVEFP-NEXT: vmov q0, q1
				; CHECK-MVEFP-NEXT: bx lr
				entry:
				%0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: sqrt_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[0]
				; CHECK-MVE-NEXT: vmov.u16 r1, q0[1]
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: movs r2, #0
				; CHECK-MVE-NEXT: vsqrt.f16 s4, s4
				; CHECK-MVE-NEXT: vmov r0, s4
				; CHECK-MVE-NEXT: vmov s4, r1
				; CHECK-MVE-NEXT: vsqrt.f16 s4, s4
				; CHECK-MVE-NEXT: vmov r1, s4
				; CHECK-MVE-NEXT: vdup.16 q1, r2
				; CHECK-MVE-NEXT: vmov.16 q1[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[2]
				; CHECK-MVE-NEXT: vmov s8, r0
				; CHECK-MVE-NEXT: vmov.16 q1[1], r1
				; CHECK-MVE-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVE-NEXT: vmov r0, s8
				; CHECK-MVE-NEXT: vmov.16 q1[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
				; CHECK-MVE-NEXT: vmov s8, r0
				; CHECK-MVE-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVE-NEXT: vmov r0, s8
				; CHECK-MVE-NEXT: vmov.16 q1[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[4]
				; CHECK-MVE-NEXT: vmov s8, r0
				; CHECK-MVE-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVE-NEXT: vmov r0, s8
				; CHECK-MVE-NEXT: vmov.16 q1[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
				; CHECK-MVE-NEXT: vmov s8, r0
				; CHECK-MVE-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVE-NEXT: vmov r0, s8
				; CHECK-MVE-NEXT: vmov.16 q1[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[6]
				; CHECK-MVE-NEXT: vmov s8, r0
				; CHECK-MVE-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVE-NEXT: vmov r0, s8
				; CHECK-MVE-NEXT: vmov.16 q1[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vsqrt.f16 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q1[7], r0
				; CHECK-MVE-NEXT: vmov q0, q1
				; CHECK-MVE-NEXT: bx lr
				;
				; CHECK-MVEFP-LABEL: sqrt_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[0]
				; CHECK-MVEFP-NEXT: vmov.u16 r1, q0[1]
				; CHECK-MVEFP-NEXT: vmov s4, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s4, s4
				; CHECK-MVEFP-NEXT: vmov r0, s4
				; CHECK-MVEFP-NEXT: vmov s4, r1
				; CHECK-MVEFP-NEXT: vsqrt.f16 s4, s4
				; CHECK-MVEFP-NEXT: vmov r1, s4
				; CHECK-MVEFP-NEXT: vmov.16 q1[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[2]
				; CHECK-MVEFP-NEXT: vmov.16 q1[1], r1
				; CHECK-MVEFP-NEXT: vmov s8, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVEFP-NEXT: vmov r0, s8
				; CHECK-MVEFP-NEXT: vmov.16 q1[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[3]
				; CHECK-MVEFP-NEXT: vmov s8, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVEFP-NEXT: vmov r0, s8
				; CHECK-MVEFP-NEXT: vmov.16 q1[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[4]
				; CHECK-MVEFP-NEXT: vmov s8, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVEFP-NEXT: vmov r0, s8
				; CHECK-MVEFP-NEXT: vmov.16 q1[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[5]
				; CHECK-MVEFP-NEXT: vmov s8, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVEFP-NEXT: vmov r0, s8
				; CHECK-MVEFP-NEXT: vmov.16 q1[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[6]
				; CHECK-MVEFP-NEXT: vmov s8, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s8, s8
				; CHECK-MVEFP-NEXT: vmov r0, s8
				; CHECK-MVEFP-NEXT: vmov.16 q1[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vsqrt.f16 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q1[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q1
				; CHECK-MVEFP-NEXT: bx lr
				entry:
				%0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @cos_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: cos_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: cos_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: cos_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl cosf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: cos_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl cosf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @sin_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: sin_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: sin_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: sin_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl sinf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: sin_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl sinf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @exp_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: exp_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: exp_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: exp_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl expf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: exp_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl expf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @exp2_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: exp2_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: exp2_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: exp2_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl exp2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: exp2_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl exp2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @log_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: log_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: log_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: log_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl logf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: log_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl logf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @log2_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: log2_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: log2_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: log2_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl log2f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: log2_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl log2f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @log10_float32_t(<4 x float> %src) {
				; CHECK-MVE-LABEL: log10_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #16
				; CHECK-MVE-NEXT: sub sp, #16
				; CHECK-MVE-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: mov r4, r0
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: vmov s18, r4
				; CHECK-MVE-NEXT: mov r0, r1
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r5
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #16
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
				;
				; CHECK-MVEFP-LABEL: log10_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r7, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #16
				; CHECK-MVEFP-NEXT: sub sp, #16
				; CHECK-MVEFP-NEXT: vstmia sp, {s0, s1, s2, s3}
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: mov r4, r0
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: ldrd r1, r5, [sp, #8]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: vmov s17, r4
				; CHECK-MVEFP-NEXT: mov r0, r1
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r5
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #16
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r7, pc}
				entry:
				%0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
				; CHECK-MVE-LABEL: log10_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #24]
				; CHECK-MVE-NEXT: ldr r0, [sp, #24]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldr r0, [sp, #28]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vdup.16 q5, r1
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[0], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.16 q5[1], r4
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldr r0, [sp, #20]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #16]
				; CHECK-MVE-NEXT: ldr r0, [sp, #16]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldr r0, [sp, #12]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #8]
				; CHECK-MVE-NEXT: ldr r0, [sp, #8]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldr r0, [sp, #4]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: ldr r0, [sp]
				; CHECK-MVE-NEXT: bl log10f
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q5[7], r0
				; CHECK-MVE-NEXT: vmov q0, q5
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: log10_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q0[1]
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #24]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #28]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[0], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q5[1], r4
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #20]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #16]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #16]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #12]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #8]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #8]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldr r0, [sp, #4]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: ldr r0, [sp]
				; CHECK-MVEFP-NEXT: bl log10f
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q5[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q5
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
				ret <8 x half> %0
				}

				define arm_aapcs_vfpcc <4 x float> @pow_float32_t(<4 x float> %src1, <4 x float> %src2) {
				; CHECK-MVE-LABEL: pow_float32_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
				; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10}
				; CHECK-MVE-NEXT: .pad #32
				; CHECK-MVE-NEXT: sub sp, #32
				; CHECK-MVE-NEXT: vstr s3, [sp, #24]
				; CHECK-MVE-NEXT: ldr r4, [sp, #24]
				; CHECK-MVE-NEXT: vstr s1, [sp, #8]
				; CHECK-MVE-NEXT: vstr s5, [sp, #12]
				; CHECK-MVE-NEXT: vstr s0, [sp]
				; CHECK-MVE-NEXT: vstr s4, [sp, #4]
				; CHECK-MVE-NEXT: vstr s7, [sp, #28]
				; CHECK-MVE-NEXT: vstr s2, [sp, #16]
				; CHECK-MVE-NEXT: vstr s6, [sp, #20]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #8]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: mov r5, r0
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: ldrd r2, r1, [sp, #16]
				; CHECK-MVE-NEXT: vmov s16, r0
				; CHECK-MVE-NEXT: ldr r6, [sp, #28]
				; CHECK-MVE-NEXT: vmov s18, r5
				; CHECK-MVE-NEXT: mov r0, r2
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s20, r0
				; CHECK-MVE-NEXT: mov r0, r4
				; CHECK-MVE-NEXT: mov r1, r6
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vmov s4, r0
				; CHECK-MVE-NEXT: vdup.32 q0, r1
				; CHECK-MVE-NEXT: vmov.f32 s0, s16
				; CHECK-MVE-NEXT: vmov.f32 s1, s18
				; CHECK-MVE-NEXT: vmov.f32 s2, s20
				; CHECK-MVE-NEXT: vmov.f32 s3, s4
				; CHECK-MVE-NEXT: add sp, #32
				; CHECK-MVE-NEXT: vpop {d8, d9, d10}
				; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
				;
				; CHECK-MVEFP-LABEL: pow_float32_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, r5, r6, lr}
				; CHECK-MVEFP-NEXT: push {r4, r5, r6, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9}
				; CHECK-MVEFP-NEXT: vpush {d8, d9}
				; CHECK-MVEFP-NEXT: .pad #32
				; CHECK-MVEFP-NEXT: sub sp, #32
				; CHECK-MVEFP-NEXT: vstr s3, [sp, #24]
				; CHECK-MVEFP-NEXT: ldr r4, [sp, #24]
				; CHECK-MVEFP-NEXT: vstr s1, [sp, #8]
				; CHECK-MVEFP-NEXT: vstr s5, [sp, #12]
				; CHECK-MVEFP-NEXT: vstr s0, [sp]
				; CHECK-MVEFP-NEXT: vstr s4, [sp, #4]
				; CHECK-MVEFP-NEXT: vstr s7, [sp, #28]
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #16]
				; CHECK-MVEFP-NEXT: vstr s6, [sp, #20]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #8]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: mov r5, r0
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: ldrd r2, r1, [sp, #16]
				; CHECK-MVEFP-NEXT: vmov s16, r0
				; CHECK-MVEFP-NEXT: ldr r6, [sp, #28]
				; CHECK-MVEFP-NEXT: vmov s17, r5
				; CHECK-MVEFP-NEXT: mov r0, r2
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s18, r0
				; CHECK-MVEFP-NEXT: mov r0, r4
				; CHECK-MVEFP-NEXT: mov r1, r6
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s19, r0
				; CHECK-MVEFP-NEXT: vmov q0, q4
				; CHECK-MVEFP-NEXT: add sp, #32
				; CHECK-MVEFP-NEXT: vpop {d8, d9}
				; CHECK-MVEFP-NEXT: pop {r4, r5, r6, pc}
				entry:
				%0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2)
				ret <4 x float> %0
				}

				define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
				; CHECK-MVE-LABEL: pow_float16_t:
				; CHECK-MVE: @ %bb.0: @ %entry
				; CHECK-MVE-NEXT: .save {r4, lr}
				; CHECK-MVE-NEXT: push {r4, lr}
				; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
				; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
				; CHECK-MVE-NEXT: .pad #64
				; CHECK-MVE-NEXT: sub sp, #64
				; CHECK-MVE-NEXT: vmov q5, q1
				; CHECK-MVE-NEXT: vmov q4, q0
				; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #56]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #60]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #56]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[1]
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r4, s0
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #48]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #52]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #48]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: movs r1, #0
				; CHECK-MVE-NEXT: vdup.16 q6, r1
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[0], r4
				; CHECK-MVE-NEXT: vmov.16 q6[1], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[2]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #40]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #44]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #40]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[2], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[3]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #32]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #36]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #32]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[3], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[4]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #24]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #28]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #24]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[4], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[5]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #16]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #20]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #16]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[5], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[6]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp, #8]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #12]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp, #8]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[6], r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q5[7]
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVE-NEXT: vmov s2, r0
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVE-NEXT: vstr s2, [sp]
				; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVE-NEXT: vstr s0, [sp, #4]
				; CHECK-MVE-NEXT: ldrd r0, r1, [sp]
				; CHECK-MVE-NEXT: bl powf
				; CHECK-MVE-NEXT: vmov s0, r0
				; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVE-NEXT: vmov r0, s0
				; CHECK-MVE-NEXT: vmov.16 q6[7], r0
				; CHECK-MVE-NEXT: vmov q0, q6
				; CHECK-MVE-NEXT: add sp, #64
				; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
				; CHECK-MVE-NEXT: pop {r4, pc}
				;
				; CHECK-MVEFP-LABEL: pow_float16_t:
				; CHECK-MVEFP: @ %bb.0: @ %entry
				; CHECK-MVEFP-NEXT: .save {r4, lr}
				; CHECK-MVEFP-NEXT: push {r4, lr}
				; CHECK-MVEFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
				; CHECK-MVEFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
				; CHECK-MVEFP-NEXT: .pad #64
				; CHECK-MVEFP-NEXT: sub sp, #64
				; CHECK-MVEFP-NEXT: vmov q5, q1
				; CHECK-MVEFP-NEXT: vmov q4, q0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q1[0]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[0]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #56]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #60]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #56]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[1]
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r4, s0
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[1]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #48]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #52]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #48]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.16 q6[0], r4
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[1], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[2]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[2]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #40]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #44]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #40]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[2], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[3]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[3]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #32]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #36]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #32]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[3], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[4]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[4]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #24]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #28]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #24]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[4], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[5]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[5]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #16]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #20]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #16]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[5], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[6]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[6]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp, #8]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #12]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp, #8]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[6], r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q5[7]
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vmov.u16 r0, q4[7]
				; CHECK-MVEFP-NEXT: vmov s2, r0
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s2, s2
				; CHECK-MVEFP-NEXT: vstr s2, [sp]
				; CHECK-MVEFP-NEXT: vcvtb.f32.f16 s0, s0
				; CHECK-MVEFP-NEXT: vstr s0, [sp, #4]
				; CHECK-MVEFP-NEXT: ldrd r0, r1, [sp]
				; CHECK-MVEFP-NEXT: bl powf
				; CHECK-MVEFP-NEXT: vmov s0, r0
				; CHECK-MVEFP-NEXT: vcvtb.f16.f32 s0, s0
				; CHECK-MVEFP-NEXT: vmov r0, s0
				; CHECK-MVEFP-NEXT: vmov.16 q6[7], r0
				; CHECK-MVEFP-NEXT: vmov q0, q6
				; CHECK-MVEFP-NEXT: add sp, #64
				; CHECK-MVEFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
				; CHECK-MVEFP-NEXT: pop {r4, pc}
				entry:
				%0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
				ret <8 x half> %0
				}

				declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
				declare <4 x float> @llvm.cos.v4f32(<4 x float>)
				declare <4 x float> @llvm.sin.v4f32(<4 x float>)
				declare <4 x float> @llvm.exp.v4f32(<4 x float>)
				declare <4 x float> @llvm.exp2.v4f32(<4 x float>)
				declare <4 x float> @llvm.log.v4f32(<4 x float>)
				declare <4 x float> @llvm.log2.v4f32(<4 x float>)
				declare <4 x float> @llvm.log10.v4f32(<4 x float>)
				declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
				declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
				declare <8 x half> @llvm.cos.v8f16(<8 x half>)
				declare <8 x half> @llvm.sin.v8f16(<8 x half>)
				declare <8 x half> @llvm.exp.v8f16(<8 x half>)
				declare <8 x half> @llvm.exp2.v8f16(<8 x half>)
				declare <8 x half> @llvm.log.v8f16(<8 x half>)
				declare <8 x half> @llvm.log2.v8f16(<8 x half>)
				declare <8 x half> @llvm.log10.v8f16(<8 x half>)
				declare <8 x half> @llvm.pow.v8f16(<8 x half>, <8 x half>)