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[ARM] Add sign and zero extend patterns for MVE
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Authored by dmgreen on Jul 2 2019, 4:56 AM.

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Summary

The vmovlb instructions can be uses to sign or zero extend registers from one size to another. This adds some patterns for them and relevant testing. The VBICIMM generation is also put behind a hasNEON check (as is already done for VORRIMM).

Code originally by David Sherwood.

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Repository
rL LLVM

Event Timeline

dmgreen created this revision.Jul 2 2019, 4:56 AM
t.p.northover accepted this revision.Jul 4 2019, 4:17 AM

Looks reasonable to me.

This revision is now accepted and ready to land.Jul 4 2019, 4:17 AM
This revision was automatically updated to reflect the committed changes.