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[ARM] MVE bitwise instruction patterns
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Authored by dmgreen on Jun 27 2019, 3:01 AM.

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Summary

This adds patterns for the simpler VAND, VORR and VEOR instructions. It also adjusts the top16Zero PatLeaf to not match on vector instructions, which can otherwise cause problems.

Code written by David Sherwood.

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Repository
rL LLVM

Event Timeline

dmgreen created this revision.Jun 27 2019, 3:01 AM
This revision is now accepted and ready to land.Jul 1 2019, 3:03 AM
This revision was automatically updated to reflect the committed changes.