[ARM] Sign_Extend_Inreg for MVE i1 types

[dmgreen]

Summary

This adds sign extends from i1 types to full registers, using pairs of shift left/rights.

[SjoerdMeijer]

LGTM

[dmgreen]

This one it turned out we didn't need because it was handled differently when we did it properly in all the predicate patches.

llvm/lib/Target/ARM/ARMInstrMVE.td

def : Pat<(v16i8 (ARMvshruImm (v16i8 MQPR:$src), imm0_7:$imm)),
             (v16i8 (MVE_VSHR_immu8 (v16i8 MQPR:$src), imm0_7:$imm))>;
 
   def : Pat<(v4i32 (ARMvshrsImm (v4i32 MQPR:$src), imm0_31:$imm)),
             (v4i32 (MVE_VSHR_imms32 (v4i32 MQPR:$src), imm0_31:$imm))>;
   def : Pat<(v8i16 (ARMvshrsImm (v8i16 MQPR:$src), imm0_15:$imm)),
             (v8i16 (MVE_VSHR_imms16 (v8i16 MQPR:$src), imm0_15:$imm))>;
   def : Pat<(v16i8 (ARMvshrsImm (v16i8 MQPR:$src), imm0_7:$imm)),
             (v16i8 (MVE_VSHR_imms8 (v16i8 MQPR:$src), imm0_7:$imm))>;
+
+  def : Pat<(sext_inreg (v4i32 MQPR:$src), v4i1),
+            (MVE_VSHR_imms32 (MVE_VSHL_immi32 MQPR:$src, 31), 31)>;
+  def : Pat<(sext_inreg (v8i16 MQPR:$src), v8i1),
+            (MVE_VSHR_imms16 (MVE_VSHL_immi16 MQPR:$src, 15), 15)>;
+  def : Pat<(sext_inreg (v16i8 MQPR:$src), v16i1),
+            (MVE_VSHR_imms8 (MVE_VSHL_immi8 MQPR:$src, 7), 7)>;
 }
 
 // end of mve_shift instructions
 
 // start of MVE Floating Point instructions
 
 class MVE_float<string iname, string suffix, dag oops, dag iops, string ops,
                 vpred_ops vpred, string cstr, list<dag> pattern=[]>

llvm/test/CodeGen/Thumb2/mve-sext.ll

 ; CHECK-LABEL: trunc_v2i64_v2i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = trunc <2 x i64> %src to <2 x i32>
   ret <2 x i32> %0
 }
 
+
+define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i1> %src) {
+; CHECK-LABEL: sext_v4i1_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vshl.i32 q0, q0, #31
+; CHECK-NEXT:    vshr.s32 q0, q0, #31
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sext <4 x i1> %src to <4 x i32>
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8i16(<8 x i1> %src) {
+; CHECK-LABEL: sext_v8i1_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vshl.i16 q0, q0, #15
+; CHECK-NEXT:    vshr.s16 q0, q0, #15
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sext <8 x i1> %src to <8 x i16>
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @sext_v16i1_v16i8(<16 x i1> %src) {
+; CHECK-LABEL: sext_v16i1_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vshl.i8 q0, q0, #7
+; CHECK-NEXT:    vshr.s8 q0, q0, #7
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sext <16 x i1> %src to <16 x i8>
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i1> %src) {
+; CHECK-LABEL: sext_v2i1_v2i64:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    vmov.32 q1[0], r0
+; CHECK-NEXT:    vmov.32 q1[1], r0
+; CHECK-NEXT:    vmov r0, s2
+; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    vmov.32 q1[2], r0
+; CHECK-NEXT:    vmov.32 q1[3], r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sext <2 x i1> %src to <2 x i64>
+  ret <2 x i64> %0
+}