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Differential D63725

[ARM] Mark math routines as non-legal for MVE
ClosedPublic

Authored by dmgreen on Jun 24 2019, 9:42 AM.

Details

Reviewers
t.p.northover
simon_tatham
samparker
SjoerdMeijer
ostannard
Commits
rG28839440352d: [ARM] Mark math routines as non-legal for MVE
rL364641: [ARM] Mark math routines as non-legal for MVE
Summary

This adds handling and tests for a number of floating point math routines.

Diff Detail

Event Timeline

dmgreen created this revision.Jun 24 2019, 9:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2019, 9:43 AM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
SjoerdMeijer accepted this revision.Jun 24 2019, 1:28 PM

looks very reasonable to me.

This revision is now accepted and ready to land.Jun 24 2019, 1:28 PM
dmgreen added a parent revision: D63595: [ARM] Mark div and rem as expand for MVE.Jun 25 2019, 5:00 AM
dmgreen added a child revision: D63861: [ARM] MVE patterns for abs and neg..Jun 27 2019, 2:49 AM
Closed by commit rL364641: [ARM] Mark math routines as non-legal for MVE (authored by dmgreen). · Explain WhyJun 28 2019, 4:18 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
9 lines
test/
CodeGen/
Thumb2/
916 lines

Diff 206243

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Lines for (MVT VT : fTypes) {
setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::FMINNUM, VT, Legal); setOperationAction(ISD::FMINNUM, VT, Legal);
setOperationAction(ISD::FMAXNUM, VT, Legal); setOperationAction(ISD::FMAXNUM, VT, Legal);
// No native support for these. // No native support for these.
setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FDIV, VT, Expand);
setOperationAction(ISD::FREM, VT, Expand); setOperationAction(ISD::FREM, VT, Expand);
setOperationAction(ISD::FSQRT, VT, Expand);
setOperationAction(ISD::FSIN, VT, Expand);
setOperationAction(ISD::FCOS, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
setOperationAction(ISD::FLOG, VT, Expand);
setOperationAction(ISD::FLOG2, VT, Expand);
setOperationAction(ISD::FLOG10, VT, Expand);
setOperationAction(ISD::FEXP, VT, Expand);
setOperationAction(ISD::FEXP2, VT, Expand);
} }
addRegisterClass(MVT::v2f64, &ARM::QPRRegClass); addRegisterClass(MVT::v2f64, &ARM::QPRRegClass);
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
setOperationAction(Opc, MVT::v2f64, Expand); setOperationAction(Opc, MVT::v2f64, Expand);
setOperationAction(ISD::BITCAST, MVT::v2f64, Legal); setOperationAction(ISD::BITCAST, MVT::v2f64, Legal);
setOperationAction(ISD::LOAD, MVT::v2f64, Legal); setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
setOperationAction(ISD::STORE, MVT::v2f64, Legal); setOperationAction(ISD::STORE, MVT::v2f64, Legal);
▲ Show 20 Lines • Show All 15,277 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fmath.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabihf -mattr=+mve.fp %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {
; CHECK-LABEL: sqrt_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsqrt.f32 s4, s0
; CHECK-NEXT: vsqrt.f32 s5, s1
; CHECK-NEXT: vsqrt.f32 s6, s2
; CHECK-NEXT: vsqrt.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {
; CHECK-LABEL: sqrt_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov s4, r0
; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vsqrt.f16 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @cos_float32_t(<4 x float> %src) {
; CHECK-LABEL: cos_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
; CHECK-LABEL: cos_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @sin_float32_t(<4 x float> %src) {
; CHECK-LABEL: sin_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
; CHECK-LABEL: sin_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @exp_float32_t(<4 x float> %src) {
; CHECK-LABEL: exp_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @exp2_float32_t(<4 x float> %src) {
; CHECK-LABEL: exp2_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp2_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @log_float32_t(<4 x float> %src) {
; CHECK-LABEL: log_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
; CHECK-LABEL: log_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @log2_float32_t(<4 x float> %src) {
; CHECK-LABEL: log2_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
; CHECK-LABEL: log2_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @log10_float32_t(<4 x float> %src) {
; CHECK-LABEL: log10_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov.f32 s21, s0
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov.f32 s20, s0
; CHECK-NEXT: vmov.f32 s0, s19
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov.f32 s23, s0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
; CHECK-LABEL: log10_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @pow_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-LABEL: pow_float32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vmov.f32 s0, s22
; CHECK-NEXT: vmov.f32 s1, s18
; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov.f32 s26, s0
; CHECK-NEXT: vmov.f32 s0, s20
; CHECK-NEXT: vmov.f32 s1, s16
; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov.f32 s24, s0
; CHECK-NEXT: vmov.f32 s0, s21
; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov.f32 s25, s0
; CHECK-NEXT: vmov.f32 s0, s23
; CHECK-NEXT: vmov.f32 s1, s19
; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov.f32 s27, s0
; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: pow_float16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov.u16 r0, q5[0]
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q6[1], r4
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q5[6]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s2
; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, pc}
entry:
%0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0
}
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
declare <4 x float> @llvm.cos.v4f32(<4 x float>)
declare <4 x float> @llvm.sin.v4f32(<4 x float>)
declare <4 x float> @llvm.exp.v4f32(<4 x float>)
declare <4 x float> @llvm.exp2.v4f32(<4 x float>)
declare <4 x float> @llvm.log.v4f32(<4 x float>)
declare <4 x float> @llvm.log2.v4f32(<4 x float>)
declare <4 x float> @llvm.log10.v4f32(<4 x float>)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
declare <8 x half> @llvm.cos.v8f16(<8 x half>)
declare <8 x half> @llvm.sin.v8f16(<8 x half>)
declare <8 x half> @llvm.exp.v8f16(<8 x half>)
declare <8 x half> @llvm.exp2.v8f16(<8 x half>)
declare <8 x half> @llvm.log.v8f16(<8 x half>)
declare <8 x half> @llvm.log2.v8f16(<8 x half>)
declare <8 x half> @llvm.log10.v8f16(<8 x half>)
declare <8 x half> @llvm.pow.v8f16(<8 x half>, <8 x half>)