[ARM] Select MVE fp add and sub

[dmgreen]

Summary

Same as integer addition, we can add simple floating point MVE addition and subtraction patterns.

Initial code by David Sherwood

[dmgreen]

Rebased for new patterns and moved next to instruction definition.

[SjoerdMeijer]

llvm/test/CodeGen/Thumb2/mve-simple-arith.ll

34

do we need to test this when we only have -mattr=+mve?

[dmgreen]

Now shows the awful code we generate from expansions when mve+fullfp16 is used (not mve.fp). The vdups will be cleared up later

[SjoerdMeijer]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

multiclass unpred_int_op_rr<SDPatternOperator opnode, string RegRegOp> {
   def i16 : Pat<(v8i16 (opnode (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
                 (v8i16 (!cast<Instruction>(RegRegOp#"i16") (v8i16 MQPR:$val1),
                          (v8i16 MQPR:$val2)))>;
   def i32 : Pat<(v4i32 (opnode (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
                 (v4i32 (!cast<Instruction>(RegRegOp#"i32") (v4i32 MQPR:$val1),
                          (v4i32 MQPR:$val2)))>;
 }
 
+multiclass unpred_fp_op_rr<SDPatternOperator opnode, string RegRegOp> {
+  def f16 : Pat<(v8f16 (opnode (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
+                (v8f16 (!cast<Instruction>(RegRegOp#"f16")
+                         (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
+  def f32 : Pat<(v4f32 (opnode (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
+                (v4f32 (!cast<Instruction>(RegRegOp#"f32")
+                         (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
+}
+
 // Arithmetic
 
 let Predicates = [HasMVEInt] in {
   defm Pat_VADDt1i        : unpred_int_op_rr<add, "VADDt1">;
   defm Pat_VSUBt1i        : unpred_int_op_rr<sub, "VSUBt1">;
 }
+
+let Predicates = [HasMVEFloat] in {
+  defm Pat_VADDfpt1       : unpred_fp_op_rr<fadd, "VADDt1">;
+  defm Pat_VSUBfpt1       : unpred_fp_op_rr<fsub, "VSUBt1">;
+}

llvm/test/CodeGen/Thumb2/mve-simple-arith.ll

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vadd.i32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = add nsw <4 x i32> %src1, %src2
   ret <4 x i32> %0
 }
 
+define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: add_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.f16 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = fadd nnan ninf nsz <8 x half> %src2, %src1
+  ret <8 x half> %0
+}
+
+define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: add_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.f32 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = fadd nnan ninf nsz <4 x float> %src2, %src1
+  ret <4 x float> %0
+}
+
 
 define arm_aapcs_vfpcc <16 x i8> @sub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
 ; CHECK-LABEL: sub_int8_t:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vsub.i8 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = sub <16 x i8> %src2, %src1

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vsub.i32 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = sub nsw <4 x i32> %src2, %src1
   ret <4 x i32> %0
 }
 
+define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: sub_float16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.f16 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = fsub nnan ninf nsz <8 x half> %src2, %src1
+  ret <8 x half> %0
+}
+
+define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: sub_float32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.f32 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = fsub nnan ninf nsz <4 x float> %src2, %src1
+  ret <4 x float> %0
+}