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Differential D62601

[AArch64][SVE2] Asm: support WHILE instructions
ClosedPublic

Authored by c-rhodes on May 29 2019, 8:35 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
chill
Commits
rG0fc3a0739850: [AArch64][SVE2] Asm: support WHILE instructions
rL362215: [AArch64][SVE2] Asm: support WHILE instructions
Summary

This is the last patch in the series adding MC layer support for the SVE2 architecture extension. Many thanks to @sdesmalen @SjoerdMeijer @rovka @chill for taking the time to review patches!

Patch adds support for the following instructions:

  • WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Event Timeline

c-rhodes created this revision.May 29 2019, 8:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 29 2019, 8:35 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar. · View Herald Transcript
c-rhodes added a parent revision: D62600: [AArch64][SVE2] Asm: support TBL/TBX instructions.May 29 2019, 8:36 AM
c-rhodes added a child revision: D62602: [AArch64][SVE2] Add CPU and arch directive tests.May 29 2019, 8:42 AM
chill accepted this revision.May 30 2019, 7:00 AM
This revision is now accepted and ready to land.May 30 2019, 7:00 AM
Closed by commit rL362215: [AArch64][SVE2] Asm: support WHILE instructions (authored by c-rhodes). · Explain WhyMay 31 2019, 2:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
15 lines
26 lines
test/
MC/
AArch64/
SVE2/
29 lines
68 lines
29 lines
68 lines
29 lines
68 lines
29 lines
68 lines
25 lines
32 lines
25 lines
32 lines

Diff 201927

lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 1,365 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE2] in {
defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>; defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>; defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>; defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>; defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
// SVE table lookup (three sources) // SVE table lookup (three sources)
defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">; defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">; defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
// SVE integer compare scalar count and limit
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">;
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">;
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">;
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi">;
defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">;
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">;
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">;
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">;
// SVE pointer conflict compare
defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">;
defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">;
} }
let Predicates = [HasSVE2AES] in { let Predicates = [HasSVE2AES] in {
// SVE2 crypto destructive binary operations // SVE2 crypto destructive binary operations
def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>; def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>;
def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>; def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>;
// SVE2 crypto unary operations // SVE2 crypto unary operations
Show All 30 Lines

lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 3,264 Lines • ▼ Show 20 Lines
multiclass sve_int_while8_rr<bits<3> opc, string asm> { multiclass sve_int_while8_rr<bits<3> opc, string asm> {
def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>; def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>;
def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>; def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>;
def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>; def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>;
def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>;
} }
class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,
PPRRegOp pprty>
: I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
asm, "\t$Pd, $Rn, $Rm",
"", []>, Sched<[]> {
bits<4> Pd;
bits<5> Rm;
bits<5> Rn;
let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64;
let Inst{21} = 0b1;
let Inst{20-16} = Rm;
let Inst{15-10} = 0b001100;
let Inst{9-5} = Rn;
let Inst{4} = rw;
let Inst{3-0} = Pd;
let Defs = [NZCV];
}
multiclass sve2_int_while_rr<bits<1> rw, string asm> {
def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>;
def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>;
def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>;
def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Fast Reduction Group // SVE Floating Point Fast Reduction Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm, class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
ZPRRegOp zprty, RegisterClass dstRegClass> ZPRRegOp zprty, RegisterClass dstRegClass>
: I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
▲ Show 20 Lines • Show All 2,410 Lines • Show Last 20 Lines

test/MC/AArch64/SVE2/whilege-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilege p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilege p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilege p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilege p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilege p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilege.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilege p15.b, xzr, x0
// CHECK-INST: whilege p15.b, xzr, x0
// CHECK-ENCODING: [0xef,0x13,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 13 20 25 <unknown>
whilege p15.b, x0, xzr
// CHECK-INST: whilege p15.b, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 3f 25 <unknown>
whilege p15.b, wzr, w0
// CHECK-INST: whilege p15.b, wzr, w0
// CHECK-ENCODING: [0xef,0x03,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 03 20 25 <unknown>
whilege p15.b, w0, wzr
// CHECK-INST: whilege p15.b, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 3f 25 <unknown>
whilege p15.h, x0, xzr
// CHECK-INST: whilege p15.h, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 7f 25 <unknown>
whilege p15.h, w0, wzr
// CHECK-INST: whilege p15.h, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 7f 25 <unknown>
whilege p15.s, x0, xzr
// CHECK-INST: whilege p15.s, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 bf 25 <unknown>
whilege p15.s, w0, wzr
// CHECK-INST: whilege p15.s, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 bf 25 <unknown>
whilege p15.d, w0, wzr
// CHECK-INST: whilege p15.d, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 ff 25 <unknown>
whilege p15.d, x0, xzr
// CHECK-INST: whilege p15.d, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 ff 25 <unknown>

test/MC/AArch64/SVE2/whilegt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilegt p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilegt p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilegt p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilegt p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilegt p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilegt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilegt p15.b, xzr, x0
// CHECK-INST: whilegt p15.b, xzr, x0
// CHECK-ENCODING: [0xff,0x13,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 20 25 <unknown>
whilegt p15.b, x0, xzr
// CHECK-INST: whilegt p15.b, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 3f 25 <unknown>
whilegt p15.b, wzr, w0
// CHECK-INST: whilegt p15.b, wzr, w0
// CHECK-ENCODING: [0xff,0x03,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 20 25 <unknown>
whilegt p15.b, w0, wzr
// CHECK-INST: whilegt p15.b, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 3f 25 <unknown>
whilegt p15.h, x0, xzr
// CHECK-INST: whilegt p15.h, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 7f 25 <unknown>
whilegt p15.h, w0, wzr
// CHECK-INST: whilegt p15.h, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 7f 25 <unknown>
whilegt p15.s, x0, xzr
// CHECK-INST: whilegt p15.s, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 bf 25 <unknown>
whilegt p15.s, w0, wzr
// CHECK-INST: whilegt p15.s, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 bf 25 <unknown>
whilegt p15.d, w0, wzr
// CHECK-INST: whilegt p15.d, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 ff 25 <unknown>
whilegt p15.d, x0, xzr
// CHECK-INST: whilegt p15.d, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 ff 25 <unknown>

test/MC/AArch64/SVE2/whilehi-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilehi p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehi p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehi p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilehi p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilehi p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilehi.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilehi p15.b, xzr, x0
// CHECK-INST: whilehi p15.b, xzr, x0
// CHECK-ENCODING: [0xff,0x1b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b 20 25 <unknown>
whilehi p15.b, x0, xzr
// CHECK-INST: whilehi p15.b, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 3f 25 <unknown>
whilehi p15.b, wzr, w0
// CHECK-INST: whilehi p15.b, wzr, w0
// CHECK-ENCODING: [0xff,0x0b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b 20 25 <unknown>
whilehi p15.b, w0, wzr
// CHECK-INST: whilehi p15.b, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 3f 25 <unknown>
whilehi p15.h, x0, xzr
// CHECK-INST: whilehi p15.h, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 7f 25 <unknown>
whilehi p15.h, w0, wzr
// CHECK-INST: whilehi p15.h, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 7f 25 <unknown>
whilehi p15.s, x0, xzr
// CHECK-INST: whilehi p15.s, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 bf 25 <unknown>
whilehi p15.s, w0, wzr
// CHECK-INST: whilehi p15.s, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 bf 25 <unknown>
whilehi p15.d, w0, wzr
// CHECK-INST: whilehi p15.d, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 ff 25 <unknown>
whilehi p15.d, x0, xzr
// CHECK-INST: whilehi p15.d, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 ff 25 <unknown>

test/MC/AArch64/SVE2/whilehs-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilehs p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehs p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehs p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilehs p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilehs p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilehs.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilehs p15.b, xzr, x0
// CHECK-INST: whilehs p15.b, xzr, x0
// CHECK-ENCODING: [0xef,0x1b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 1b 20 25 <unknown>
whilehs p15.b, x0, xzr
// CHECK-INST: whilehs p15.b, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 3f 25 <unknown>
whilehs p15.b, wzr, w0
// CHECK-INST: whilehs p15.b, wzr, w0
// CHECK-ENCODING: [0xef,0x0b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 0b 20 25 <unknown>
whilehs p15.b, w0, wzr
// CHECK-INST: whilehs p15.b, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 3f 25 <unknown>
whilehs p15.h, x0, xzr
// CHECK-INST: whilehs p15.h, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 7f 25 <unknown>
whilehs p15.h, w0, wzr
// CHECK-INST: whilehs p15.h, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 7f 25 <unknown>
whilehs p15.s, x0, xzr
// CHECK-INST: whilehs p15.s, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 bf 25 <unknown>
whilehs p15.s, w0, wzr
// CHECK-INST: whilehs p15.s, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 bf 25 <unknown>
whilehs p15.d, w0, wzr
// CHECK-INST: whilehs p15.d, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 ff 25 <unknown>
whilehs p15.d, x0, xzr
// CHECK-INST: whilehs p15.d, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 ff 25 <unknown>

test/MC/AArch64/SVE2/whilerw-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilerw p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilerw.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilerw p15.b, x30, x30
// CHECK-INST: whilerw p15.b, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0x3e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 3e 25 <unknown>
whilerw p15.h, x30, x30
// CHECK-INST: whilerw p15.h, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0x7e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 7e 25 <unknown>
whilerw p15.s, x30, x30
// CHECK-INST: whilerw p15.s, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0xbe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 be 25 <unknown>
whilerw p15.d, x30, x30
// CHECK-INST: whilerw p15.d, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0xfe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 fe 25 <unknown>

test/MC/AArch64/SVE2/whilewr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilewr p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilewr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilewr p15.b, x30, x30
// CHECK-INST: whilewr p15.b, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0x3e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 3e 25 <unknown>
whilewr p15.h, x30, x30
// CHECK-INST: whilewr p15.h, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0x7e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 7e 25 <unknown>
whilewr p15.s, x30, x30
// CHECK-INST: whilewr p15.s, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0xbe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 be 25 <unknown>
whilewr p15.d, x30, x30
// CHECK-INST: whilewr p15.d, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0xfe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 fe 25 <unknown>