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[AArch64][SVE2] Asm: support SVE2 store instructions
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Authored by c-rhodes on May 29 2019, 8:21 AM.

Details

Summary

Patch adds support for the following instructions:

  • STNT1B, STNT1H, STNT1S, STNT1D

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Repository
rL LLVM

Event Timeline

c-rhodes created this revision.May 29 2019, 8:21 AM
chill added inline comments.May 29 2019, 10:49 AM
test/MC/AArch64/SVE/stnt1b-diagnostics.s
26 ↗(On Diff #201921)

Is my understanding correct that we're interpreting an alias in a different way, but this happens only on error?

c-rhodes added inline comments.May 30 2019, 2:16 AM
test/MC/AArch64/SVE/stnt1b-diagnostics.s
26 ↗(On Diff #201921)

The error has changed because a vector plus scalar form of stnt1b has been added and it's being matched differently.

stnt1b z0.s, p0, [x0] is now valid until the base [x0], the following output from the asm-matcher might better explain it:

Before

echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher
        .text
AsmMatcher: found 6 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:8: error: invalid element width
stnt1b z0.s, p0, [x0]
       ^

After

echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher                                                                                                               
        .text
AsmMatcher: found 16 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:19: error: invalid operand for instruction
stnt1b z0.s, p0, [x0]
                  ^
chill accepted this revision.May 30 2019, 2:48 AM

LGTM

This revision is now accepted and ready to land.May 30 2019, 2:48 AM
This revision was automatically updated to reflect the committed changes.