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[AArch64][SVE2] Asm: add saturating add/sub instructions
ClosedPublic

Authored by c-rhodes on May 20 2019, 3:00 AM.

Details

Summary

Patch adds support for the following instructions:

  • SQADD, UQADD, SUQADD, USQADD
  • SQSUB, UQSUB, SQSUBR, UQSUBR

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Repository
rL LLVM

Event Timeline

c-rhodes created this revision.May 20 2019, 3:00 AM
chill added a subscriber: chill.May 22 2019, 7:59 AM
chill added inline comments.
test/MC/AArch64/SVE2/sqadd.s
12 ↗(On Diff #200229)

The encoding does not look right.

In https://reviews.llvm.org/D62000 there's this bit:

class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
                          ZPRRegOp zprty>
...
  let Inst{21-20} = 0b01;
  let Inst{20-16} = opc{5-1};
...

which has overlapping bit 20.

c-rhodes added inline comments.May 22 2019, 9:20 AM
test/MC/AArch64/SVE2/sqadd.s
12 ↗(On Diff #200229)

Good spot, bit 20 shouldn't overlap there, that should be:

let Inst{21}    = 0b0;
let Inst{20-16} = opc{5-1};

I believe the encodings are still correct however as bit 20 is defined by the opc bits and this overwrites the earlier error of setting bit 20 to 0. I've checked all the encodings for instructions defined by sve2_int_arith_pred and compared against other implementations and can't see any issues.

I'll create patch for the above to address the overlapping bit 20. Thanks for spotting this!

chill accepted this revision.May 23 2019, 2:50 AM
This revision is now accepted and ready to land.May 23 2019, 2:50 AM
c-rhodes marked an inline comment as done.May 24 2019, 1:45 AM
c-rhodes added inline comments.
test/MC/AArch64/SVE2/sqadd.s
12 ↗(On Diff #200229)

Removed overlapping bit in: https://reviews.llvm.org/D62292

This revision was automatically updated to reflect the committed changes.