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[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
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Authored by c-rhodes on May 24 2019, 6:23 AM.

Details

Summary

Patch adds support for the following instructions:

  • EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR

Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Repository
rL LLVM

Event Timeline

c-rhodes created this revision.May 24 2019, 6:23 AM
This revision is now accepted and ready to land.May 28 2019, 12:19 AM
This revision was automatically updated to reflect the committed changes.