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Differential D62602

[AArch64][SVE2] Add CPU and arch directive tests
ClosedPublic

Authored by c-rhodes on May 29 2019, 8:42 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
chill
Commits
rG3901dd3e4126: [AArch64][SVE2] Add CPU and arch directive tests
rL362378: [AArch64][SVE2] Add CPU and arch directive tests
Summary

This patch adds tests for directives .arch, .arch_extension and .cpu for
all features defined in Arm SVE2 architecture extension.

Diff Detail

Repository
rL LLVM

Event Timeline

c-rhodes created this revision.May 29 2019, 8:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 29 2019, 8:42 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar. · View Herald Transcript
c-rhodes added a parent revision: D62601: [AArch64][SVE2] Asm: support WHILE instructions.May 29 2019, 8:42 AM
chill added inline comments.May 30 2019, 7:24 AM
test/MC/AArch64/SVE2/directive-arch-negative.s
3 ↗(On Diff #201937)

Just removing the +nosve2 part would still make the test pass. It looks to me that -mattr=+sve2 should be added to the command lime and the test split in five separate files, or otherwise reset arch between test cases.

test/MC/AArch64/SVE2/directive-arch_extension-negative.s
3 ↗(On Diff #201937)

Likewise here, removing .arch_extension nosve2 (resp. adding it) has no effect on the test outcome.

c-rhodes marked an inline comment as done.May 31 2019, 1:42 AM
c-rhodes added inline comments.
test/MC/AArch64/SVE2/directive-arch-negative.s
3 ↗(On Diff #201937)

Fair point, I don't think separate tests in general for .arch/.arch_extension/.cpu etc scales very well and -mattr=+sve2 doesn't enable all SVE2 extensions, so I think enabling/disabling arch between tests cases makes most sense, e.g.:

.arch armv8-a+sve2
.arch armv8-a+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b

.arch armv8-a+sve2-aes
.arch armv8-a+nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
test/MC/AArch64/SVE2/directive-arch_extension-negative.s
3 ↗(On Diff #201937)

I can take the same approach as above if you think that makes sense

c-rhodes marked an inline comment as not done.May 31 2019, 1:42 AM
chill added inline comments.May 31 2019, 3:25 AM
test/MC/AArch64/SVE2/directive-arch-negative.s
3 ↗(On Diff #201937)

IMHO, removing an arch extension can only be tested if the architecture included the extension by default.

The approaches above work due to a bug (https://bugs.llvm.org/show_bug.cgi?id=32873), but I guess that's
as good as it gets, so let's go with your variant.

c-rhodes updated this revision to Diff 202683.Jun 3 2019, 3:12 AM

Addressed Momchil's comments: explicitly enable/disable arch features in negative directive tests.

chill accepted this revision.Jun 3 2019, 3:21 AM
This revision is now accepted and ready to land.Jun 3 2019, 3:21 AM
Closed by commit rL362378: [AArch64][SVE2] Add CPU and arch directive tests (authored by c-rhodes). · Explain WhyJun 3 2019, 3:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 202686

llvm/trunk/test/MC/AArch64/SVE2/directive-arch-negative.s

// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch armv8-a+sve2
.arch armv8-a+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.arch armv8-a+sve2-aes
.arch armv8-a+nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.arch armv8-a+sve2-sm4
.arch armv8-a+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch armv8-a+sve2-sha3
.arch armv8-a+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch armv8-a+bitperm
.arch armv8-a+nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

llvm/trunk/test/MC/AArch64/SVE2/directive-arch.s

// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch armv8-a+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.arch armv8-a+sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.arch armv8-a+sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.arch armv8-a+sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.arch armv8-a+bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s

llvm/trunk/test/MC/AArch64/SVE2/directive-arch_extension-negative.s

// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension sve2
.arch_extension nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.arch_extension sve2-aes
.arch_extension nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.arch_extension sve2-sm4
.arch_extension nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch_extension sve2-sha3
.arch_extension nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch_extension bitperm
.arch_extension nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

llvm/trunk/test/MC/AArch64/SVE2/directive-arch_extension.s

// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.arch_extension sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.arch_extension sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.arch_extension sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.arch_extension bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s

llvm/trunk/test/MC/AArch64/SVE2/directive-cpu-negative.s

// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.cpu generic+sve2
.cpu generic+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.cpu generic+sve2-aes
.cpu generic+nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.cpu generic+sve2-sm4
.cpu generic+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.cpu generic+sve2-sha3
.cpu generic+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.cpu generic+bitperm
.cpu generic+nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

llvm/trunk/test/MC/AArch64/SVE2/directive-cpu.s

// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.cpu generic+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.cpu generic+sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.cpu generic+sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.cpu generic+sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.cpu generic+bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s