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Differential D62387

[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
ClosedPublic

Authored by c-rhodes on May 24 2019, 6:23 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
chill
Commits
rG6c04ef3d48ab: [AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
rL361936: [AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
Summary

Patch adds support for the following instructions:

  • EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR

Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Repository
rL LLVM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
11 lines
70 lines
test/
MC/
AArch64/
SVE2/
39 lines
52 lines
39 lines
30 lines
39 lines
30 lines
39 lines
30 lines
39 lines
52 lines
39 lines
30 lines
60 lines
72 lines

Diff 201843

llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 1,307 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE2] in {
def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">; def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
// SVE2 floating-point multiply-add long // SVE2 floating-point multiply-add long
def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">; def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">; def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">; def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">; def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
// SVE2 bitwise ternary operations
defm EOR3_ZZZZ_D : sve2_int_bitwise_ternary_op<0b000, "eor3">;
defm BCAX_ZZZZ_D : sve2_int_bitwise_ternary_op<0b010, "bcax">;
def BSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b001, "bsl">;
def BSL1N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b011, "bsl1n">;
def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">;
def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">;
// sve_int_rotate_imm
defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">;
// Predicated shifts // Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
} }
Show All 36 Lines

llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 2,858 Lines • ▼ Show 20 Linesmulticlass sve_int_bin_cons_log<bits<2> opc, string asm> {
def : InstAlias<asm # "\t$Zd, $Zn, $Zm", def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>; (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm", def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>; (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm", def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>; (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
} }
class sve2_int_bitwise_ternary_op_d<bits<3> opc, string asm>
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk),
asm, "\t$Zdn, $_Zdn, $Zm, $Zk",
"",
[]>, Sched<[]> {
bits<5> Zdn;
bits<5> Zk;
bits<5> Zm;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = opc{2-1};
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-11} = 0b00111;
let Inst{10} = opc{0};
let Inst{9-5} = Zk;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_bitwise_ternary_op<bits<3> opc, string asm> {
def NAME : sve2_int_bitwise_ternary_op_d<opc, asm>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>;
}
class sve2_int_rotate_right_imm<bits<4> tsz8_64, string asm,
ZPRRegOp zprty, Operand immtype>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm),
asm, "\t$Zdn, $_Zdn, $Zm, $imm",
"",
[]>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
bits<6> imm;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = tsz8_64{3-2};
let Inst{21} = 0b1;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-10} = 0b001101;
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_rotate_right_imm<string asm> {
def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>;
def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> {
let Inst{20-19} = imm{4-3};
}
def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> {
let Inst{22} = imm{5};
let Inst{20-19} = imm{4-3};
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Integer Wide Immediate - Predicated Group // SVE Integer Wide Immediate - Predicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype, class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype,
string asm, ZPRRegOp zprty> string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8), : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8),
asm, "\t$Zd, $Pg/m, $imm8", asm, "\t$Zd, $Pg/m, $imm8",
▲ Show 20 Lines • Show All 2,591 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE2/bcax-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bcax z0.b, z0.b, z1.s, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.b, z0.b, z1.s, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bcax z0.h, z0.h, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.h, z0.h, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bcax z0.d, z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.d, z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bcax z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bcax z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bcax z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bcax z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/bcax.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bcax z29.d, z29.d, z30.d, z31.d
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
// --------------------------------------------------------------------------//
// Test aliases.
bcax z29.b, z29.b, z30.b, z31.b
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
bcax z29.h, z29.h, z30.h, z31.h
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
bcax z29.s, z29.s, z30.s, z31.s
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bcax z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bcax z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3b 7e 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/bsl-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/bsl.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0x21,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c 21 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f 3e 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/bsl1n-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl1n z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl1n z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl1n z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl1n z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl1n z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/bsl1n.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0x61,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c 61 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl1n z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl1n z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f 7e 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/bsl2n-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl2n z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl2n z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl2n z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl2n z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl2n z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/bsl2n.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0xa1,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c a1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl2n z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl2n z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0xbe,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f be 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/eor3-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
eor3 z0.b, z0.b, z1.s, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.b, z0.b, z1.s, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor3 z0.h, z0.h, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.h, z0.h, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor3 z0.d, z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.d, z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
eor3 z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eor3 z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eor3 z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/eor3.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
// --------------------------------------------------------------------------//
// Test aliases.
eor3 z29.b, z29.b, z30.b, z31.b
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
eor3 z29.h, z29.h, z30.h, z31.h
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
eor3 z29.s, z29.s, z30.s, z31.s
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
eor3 z31.d, z31.d, z30.d, z29.d
// CHECK-INST: eor3 z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3b 3e 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/nbsl-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
nbsl z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nbsl z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nbsl z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
nbsl z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: nbsl z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
nbsl z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/nbsl.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-INST: nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0xe1,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c e1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
nbsl z31.d, z31.d, z30.d, z29.d
// CHECK-INST: nbsl z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0xfe,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f fe 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/xar-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
xar z30.b, z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: xar z30.b, z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z18.b, z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: xar z18.b, z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z26.h, z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: xar z26.h, z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z25.h, z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: xar z25.h, z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z17.s, z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: xar z17.s, z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z0.s, z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: xar z0.s, z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z4.d, z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: xar z4.d, z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z26.d, z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: xar z26.d, z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
xar z0.b, z0.b , z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: xar z0.b, z0.b , z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
xar z0.d, z0.d, z1.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: xar z0.d, z0.d, z1.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/xar.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
xar z0.b, z0.b, z1.b, #1
// CHECK-INST: xar z0.b, z0.b, z1.b, #1
// CHECK-ENCODING: [0x20,0x34,0x2f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 2f 04 <unknown>
xar z31.b, z31.b, z30.b, #8
// CHECK-INST: xar z31.b, z31.b, z30.b, #8
// CHECK-ENCODING: [0xdf,0x37,0x28,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 28 04 <unknown>
xar z0.h, z0.h, z1.h, #1
// CHECK-INST: xar z0.h, z0.h, z1.h, #1
// CHECK-ENCODING: [0x20,0x34,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 3f 04 <unknown>
xar z31.h, z31.h, z30.h, #16
// CHECK-INST: xar z31.h, z31.h, z30.h, #16
// CHECK-ENCODING: [0xdf,0x37,0x30,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 30 04 <unknown>
xar z0.s, z0.s, z1.s, #1
// CHECK-INST: xar z0.s, z0.s, z1.s, #1
// CHECK-ENCODING: [0x20,0x34,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 7f 04 <unknown>
xar z31.s, z31.s, z30.s, #32
// CHECK-INST: xar z31.s, z31.s, z30.s, #32
// CHECK-ENCODING: [0xdf,0x37,0x60,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 60 04 <unknown>
xar z0.d, z0.d, z1.d, #1
// CHECK-INST: xar z0.d, z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0x34,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 ff 04 <unknown>
xar z31.d, z31.d, z30.d, #64
// CHECK-INST: xar z31.d, z31.d, z30.d, #64
// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 a0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
xar z31.d, z31.d, z30.d, #64
// CHECK-INST: xar z31.d, z31.d, z30.d, #64
// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 a0 04 <unknown>