[AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add

[c-rhodes]

Summary

Patch adds support for the indexed and unpredicated vectors forms of the
FMLALB, FMLALT, FMLSLB and FMLSLT instructions.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

[chill]

test/MC/AArch64/SVE/movprfx-diagnostics.s

114

Stray patch?

[c-rhodes]

test/MC/AArch64/SVE/movprfx-diagnostics.s

114

This is just testing indexed + movprfxable gives a diagnostic. I understand it appears to be a rogue patch given the instruction is unrelated but the reason for adding it here was we noticed there were no tests for this instruction form in movprfx-diagnostics, initially thinking indexed + movprfxable was new to SVE2 until realising the SVE SDOT instruction is similar, so a test was added for that.

[chill]

test/MC/AArch64/SVE2/fmlalb-diagnostics.s

42

Missing invalid width tests for vectors (non-indexed) version, e.g.:

fmlalb z0.s, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

Likewise for fmlslb, fmlslt, and fmlalt.

[chill]

LGTM. But, please, consider the extra tests.

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE2] in {
 
   // SVE2 floating-point pairwise operations
   defm FADDP_ZPmZZ   : sve2_fp_pairwise_pred<0b000, "faddp">;
   defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">;
   defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">;
   defm FMAXP_ZPmZZ   : sve2_fp_pairwise_pred<0b110, "fmaxp">;
   defm FMINP_ZPmZZ   : sve2_fp_pairwise_pred<0b111, "fminp">;
 
+  // SVE2 floating-point multiply-add long (indexed)
+  def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
+  def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
+  def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
+  def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
+
+  // SVE2 floating-point multiply-add long
+  def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
+  def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
+  def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
+  def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
+
   // Predicated shifts
   defm SQSHL_ZPmI  : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
   defm UQSHL_ZPmI  : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
   defm SRSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
   defm URSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
   defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
 }
 

lib/Target/AArch64/SVEInstrFormats.td

 
 multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
   def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
   def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
   def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
 }
 
 //===----------------------------------------------------------------------===//
+// SVE2 Floating Point Widening Multiply-Add - Indexed Group
+//===----------------------------------------------------------------------===//
+
+class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
+                        VectorIndexH:$iop),
+  asm, "\t$Zda, $Zn, $Zm$iop",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
+  bits<3> Zm;
+  bits<3> iop;
+  let Inst{31-21} = 0b01100100101;
+  let Inst{20-19} = iop{2-1};
+  let Inst{18-16} = Zm;
+  let Inst{15-14} = 0b01;
+  let Inst{13}    = opc{1};
+  let Inst{12}    = 0b0;
+  let Inst{11}    = iop{0};
+  let Inst{10}    = opc{0};
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = Destructive;
+  let ElementSize = ElementSizeNone;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE2 Floating Point Widening Multiply-Add Group
+//===----------------------------------------------------------------------===//
+
+class sve2_fp_mla_long<bits<2> opc, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
+  asm, "\t$Zda, $Zn, $Zm",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
+  bits<5> Zm;
+  let Inst{31-21} = 0b01100100101;
+  let Inst{20-16} = Zm;
+  let Inst{15-14} = 0b10;
+  let Inst{13}    = opc{1};
+  let Inst{12-11} = 0b00;
+  let Inst{10}    = opc{0};
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = Destructive;
+  let ElementSize = ElementSizeNone;
+}
+
+//===----------------------------------------------------------------------===//
 // SVE Stack Allocation Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_arith_vl<bit opc, string asm>
 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
   asm, "\t$Rd, $Rn, $imm6",
   "",
   []>, Sched<[]> {

test/MC/AArch64/SVE/movprfx-diagnostics.s

 movprfx z0, z1
 mla z0.d, p0/m, z0.d, z2.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
 // CHECK-NEXT: mla z0.d, p0/m, z0.d, z2.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Destination used in other operand (ternary + indexed)
+
+movprfx z0, z1
+sdot z0.s, z1.b, z0.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
+// CHECK-NEXT: sdot z0.s, z1.b, z0.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Different general predicate (unary)
 
 movprfx z0.d, p0/m, z1.d
 abs z0.d, p1/m, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate
 // CHECK-NEXT: abs z0.d, p1/m, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

test/MC/AArch64/SVE2/fmlalb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlalb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlalb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlalb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlalb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlalb  z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalb  z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlalb  z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalb  z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlalb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlalb z29.s, z30.h, z31.h
+// CHECK-INST: fmlalb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+
+fmlalb z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlalb z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x40,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 40 a7 64 <unknown>
+
+fmlalb z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlalb z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 4b bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx  z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlalb z29.s, z30.h, z31.h
+// CHECK-INST: fmlalb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlalb z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlalb z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x48,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 48 bf 64 <unknown>

test/MC/AArch64/SVE2/fmlalt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlalt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlalt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlalt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlalt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlalt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlalt  z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalt  z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlalt  z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlalt  z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlalt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlalt z29.s, z30.h, z31.h
+// CHECK-INST: fmlalt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+
+fmlalt z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlalt z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x44,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 44 a7 64 <unknown>
+
+fmlalt z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlalt z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 4f bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx  z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlalt z29.s, z30.h, z31.h
+// CHECK-INST: fmlalt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlalt z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlalt z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x4c,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 4c bf 64 <unknown>

test/MC/AArch64/SVE2/fmlslb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlslb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlslb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlslb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlslb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlslb  z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslb  z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlslb  z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslb  z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlslb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlslb z29.s, z30.h, z31.h
+// CHECK-INST: fmlslb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+
+fmlslb z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlslb z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x60,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 60 a7 64 <unknown>
+
+fmlslb z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlslb z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 6b bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx  z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlslb z29.s, z30.h, z31.h
+// CHECK-INST: fmlslb z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlslb z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlslb z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x68,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 68 bf 64 <unknown>

test/MC/AArch64/SVE2/fmlslt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+fmlslt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlslt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+fmlslt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fmlslt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlslt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z29.s, p0/z, z7.s
+fmlslt  z29.s, z30.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslt  z29.s, z30.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.s, p0/z, z7.s
+fmlslt  z0.s, z1.h, z7.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: fmlslt  z0.s, z1.h, z7.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlslt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+fmlslt z29.s, z30.h, z31.h
+// CHECK-INST: fmlslt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+
+fmlslt z0.s, z1.h, z7.h[0]
+// CHECK-INST: fmlslt z0.s, z1.h, z7.h[0]
+// CHECK-ENCODING: [0x20,0x64,0xa7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 64 a7 64 <unknown>
+
+fmlslt z30.s, z31.h, z7.h[7]
+// CHECK-INST: fmlslt z30.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: fe 6f bf 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z29, z28
+// CHECK-INST: movprfx  z29, z28
+// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+
+fmlslt z29.s, z30.h, z31.h
+// CHECK-INST: fmlslt z29.s, z30.h, z31.h
+// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+fmlslt z21.s, z1.h, z7.h[7]
+// CHECK-INST: fmlslt z21.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x35,0x6c,0xbf,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 6c bf 64 <unknown>