[AArch64][SVE2] Asm: add saturating add/sub instructions

[c-rhodes]

Summary

Patch adds support for the following instructions:

• SQADD, UQADD, SUQADD, USQADD
• SQSUB, UQSUB, SQSUBR, UQSUBR

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

[chill]

test/MC/AArch64/SVE2/sqadd.s

12

The encoding does not look right.

In https://reviews.llvm.org/D62000 there's this bit:

class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
                          ZPRRegOp zprty>
...
  let Inst{21-20} = 0b01;
  let Inst{20-16} = opc{5-1};
...

which has overlapping bit 20.

[c-rhodes]

test/MC/AArch64/SVE2/sqadd.s

12

Good spot, bit 20 shouldn't overlap there, that should be:

let Inst{21}    = 0b0;
let Inst{20-16} = opc{5-1};

I believe the encodings are still correct however as bit 20 is defined by the opc bits and this overwrites the earlier error of setting bit 20 to 0. I've checked all the encodings for instructions defined by sve2_int_arith_pred and compared against other implementations and can't see any issues.

I'll create patch for the above to address the overlapping bit 20. Thanks for spotting this!

[c-rhodes]

test/MC/AArch64/SVE2/sqadd.s

12

Removed overlapping bit in: https://reviews.llvm.org/D62292