[CodeGen] Add lrint/llrint builtins

[zatrazz]

Summary

This patch add the ISD::LRINT and ISD::LLRINT along with new
intrinsics. The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an integer.

The idea is to optimize lrint/llrint generation for AArch64
in a subsequent patch. Current semantic is just route it to libm
symbol.

(This is patch is similar to D61390).

[craig.topper]

Can we do this with 2 intrinsics with overloaded result types as I've done for lround/llround in D62026?

[zatrazz]

In D62017#1505300, @craig.topper wrote:

Can we do this with 2 intrinsics with overloaded result types as I've done for lround/llround in D62026?

We can and I will update this patch accordingly.

[zatrazz]

Updated patch based on D62026.

[craig.topper]

LGTM

[arsenm]

What is the point of these intrinsics exactly? It seems like it's just copying the libm function names, despite them only differing in the return integer type. Why can't this be accomplished with adding type mangling to the regular rint intrinsic?

[craig.topper]

In D62017#2180847, @arsenm wrote:

What is the point of these intrinsics exactly? It seems like it's just copying the libm function names, despite them only differing in the return integer type. Why can't this be accomplished with adding type mangling to the regular rint intrinsic?

I think the primary complication is that we need to know what libcall to emit if the target doesn't natively support them. The backend doesn't know how to map from IR type "long" or "long long" to generate the right libcall.

[arsenm]

In D62017#2180847, @arsenm wrote:

What is the point of these intrinsics exactly? It seems like it's just copying the libm function names, despite them only differing in the return integer type. Why can't this be accomplished with adding type mangling to the regular rint intrinsic?

Not the regular rint intrinsic, which returns float, but between lrint and llrint

[arsenm]

In D62017#2180852, @craig.topper wrote:

In D62017#2180847, @arsenm wrote:

What is the point of these intrinsics exactly? It seems like it's just copying the libm function names, despite them only differing in the return integer type. Why can't this be accomplished with adding type mangling to the regular rint intrinsic?

I think the primary complication is that we need to know what libcall to emit if the target doesn't natively support them. The backend doesn't know how to map from IR type "long" or "long long" to generate the right libcall.

But does that matter? What does the right library call really mean? I don't think the purpose of the math intrinsics is to wrap libm. Intrinsics should provide functionality independently of whatever the platform libm does. The backend is responsible for figuring out how to codegen any intrinsics which may or may not involve a platform provided library call.

[craig.topper]

In D62017#2180856, @arsenm wrote:

In D62017#2180852, @craig.topper wrote:

In D62017#2180847, @arsenm wrote:

What is the point of these intrinsics exactly? It seems like it's just copying the libm function names, despite them only differing in the return integer type. Why can't this be accomplished with adding type mangling to the regular rint intrinsic?

I think the primary complication is that we need to know what libcall to emit if the target doesn't natively support them. The backend doesn't know how to map from IR type "long" or "long long" to generate the right libcall.

But does that matter? What does the right library call really mean? I don't think the purpose of the math intrinsics is to wrap libm. Intrinsics should provide functionality independently of whatever the platform libm does. The backend is responsible for figuring out how to codegen any intrinsics which may or may not involve a platform provided library call.

I'm not sure they should have been intrinsics versus just matching LibFunc_lrint and LibFunc_llrint in SelectionDAGBuilder. Most targets are using the default Expand operation in LegalizeDAG so that still needs the ISD node to carry the function name to reverse back to library call name. The mapping from IR type to long vs long long is target and OS dependent. Unless we make SelectionDAGBuilder only use an ISD node if the target has the operation as Legal/Custom.

[arsenm]

In D62017#2180861, @craig.topper wrote:

so that still needs the ISD node to carry the function name to reverse back to library call name. The mapping from IR type to long vs long long is target and OS dependent.

I don't understand why you can't derive the call name from the triple

llvm/docs/LangRef.rst

 The argument is a floating-point number and return is an integer type.
 
 Semantics:
 """"""""""
 
 This function returns the same values as the libm ``llround``
 functions would, but without setting errno.
 
+'``llvm.lrint.*``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+This is an overloaded intrinsic. You can use ``llvm.lrint`` on any
+floating-point type. Not all targets support all types however.
+
+::
+
+      declare i32 @llvm.lrint.i32.f32(float %Val)
+      declare i32 @llvm.lrint.i32.f64(double %Val)
+      declare i32 @llvm.lrint.i32.f80(float %Val)
+      declare i32 @llvm.lrint.i32.f128(double %Val)
+      declare i32 @llvm.lrint.i32.ppcf128(double %Val)
+
+      declare i64 @llvm.lrint.i64.f32(float %Val)
+      declare i64 @llvm.lrint.i64.f64(double %Val)
+      declare i64 @llvm.lrint.i64.f80(float %Val)
+      declare i64 @llvm.lrint.i64.f128(double %Val)
+      declare i64 @llvm.lrint.i64.ppcf128(double %Val)
+
+Overview:
+"""""""""
+
+The '``llvm.lrint.*``' intrinsics returns the operand rounded to the
+nearest integer.
+
+Arguments:
+""""""""""
+
+The argument is a floating-point number and return is an integer type.
+
+Semantics:
+""""""""""
+
+This function returns the same values as the libm ``lrint``
+functions would, but without setting errno.
+
+'``llvm.llrint.*``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+This is an overloaded intrinsic. You can use ``llvm.llrint`` on any
+floating-point type. Not all targets support all types however.
+
+::
+
+      declare i64 @llvm.llrint.i64.f32(float %Val)
+      declare i64 @llvm.llrint.i64.f64(double %Val)
+      declare i64 @llvm.llrint.i64.f80(float %Val)
+      declare i64 @llvm.llrint.i64.f128(double %Val)
+      declare i64 @llvm.llrint.i64.ppcf128(double %Val)
+
+Overview:
+"""""""""
+
+The '``llvm.llrint.*``' intrinsics returns the operand rounded to the
+nearest integer.
+
+Arguments:
+""""""""""
+
+The argument is a floating-point number and return is an integer type.
+
+Semantics:
+""""""""""
+
+This function returns the same values as the libm ``llrint``
+functions would, but without setting errno.
+
 Bit Manipulation Intrinsics
 ---------------------------
 
 LLVM provides intrinsics for a few important bit manipulation
 operations. These allow efficient code generation for some algorithms.
 
 '``llvm.bitreverse.*``' Intrinsics
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

llvm/include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
     FP16_TO_FP, FP_TO_FP16,
 
     /// Perform various unary floating-point operations inspired by libm. For
     /// FPOWI, the result is undefined if if the integer operand doesn't fit
     /// into 32 bits.
     FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW,
     FLOG, FLOG2, FLOG10, FEXP, FEXP2,
     FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
-    LROUND, LLROUND,
+    LROUND, LLROUND, LRINT, LLRINT,
 
     /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
     /// values.
     //
     /// In the case where a single input is a NaN (either signaling or quiet),
     /// the non-NaN input is returned.
     ///
     /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.

llvm/include/llvm/IR/Intrinsics.td

let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
   def int_rint  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_nearbyint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_round : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_canonicalize : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>],
                                    [IntrNoMem]>;
 
   def int_lround : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
   def int_llround : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_lrint : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_llrint : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
 }
 
 def int_minnum : Intrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, Commutative]
 >;
 def int_maxnum : Intrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],

llvm/include/llvm/IR/RuntimeLibcalls.def

 HANDLE_LIBCALL(LROUND_F80, "lroundl")
 HANDLE_LIBCALL(LROUND_F128, "lroundl")
 HANDLE_LIBCALL(LROUND_PPCF128, "lroundl")
 HANDLE_LIBCALL(LLROUND_F32, "llroundf")
 HANDLE_LIBCALL(LLROUND_F64, "llround")
 HANDLE_LIBCALL(LLROUND_F80, "llroundl")
 HANDLE_LIBCALL(LLROUND_F128, "llroundl")
 HANDLE_LIBCALL(LLROUND_PPCF128, "llroundl")
+HANDLE_LIBCALL(LRINT_F32, "lrintf")
+HANDLE_LIBCALL(LRINT_F64, "lrint")
+HANDLE_LIBCALL(LRINT_F80, "lrintl")
+HANDLE_LIBCALL(LRINT_F128, "lrintl")
+HANDLE_LIBCALL(LRINT_PPCF128, "lrintl")
+HANDLE_LIBCALL(LLRINT_F32, "llrintf")
+HANDLE_LIBCALL(LLRINT_F64, "llrint")
+HANDLE_LIBCALL(LLRINT_F80, "llrintl")
+HANDLE_LIBCALL(LLRINT_F128, "llrintl")
+HANDLE_LIBCALL(LLRINT_PPCF128, "llrintl")
 
 // Conversion
 HANDLE_LIBCALL(FPEXT_F32_PPCF128, "__gcc_stoq")
 HANDLE_LIBCALL(FPEXT_F64_PPCF128, "__gcc_dtoq")
 HANDLE_LIBCALL(FPEXT_F80_F128, "__extendxftf2")
 HANDLE_LIBCALL(FPEXT_F64_F128, "__extenddftf2")
 HANDLE_LIBCALL(FPEXT_F32_F128, "__extendsftf2")
 HANDLE_LIBCALL(FPEXT_F32_F64, "__extendsfdf2")

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

if (Action != TargetLowering::Promote)
       Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
     break;
   case ISD::FP_TO_FP16:
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
   case ISD::EXTRACT_VECTOR_ELT:
   case ISD::LROUND:
   case ISD::LLROUND:
+  case ISD::LRINT:
+  case ISD::LLRINT:
     Action = TLI.getOperationAction(Node->getOpcode(),
                                     Node->getOperand(0).getValueType());
     break;
   case ISD::FP_ROUND_INREG:
   case ISD::SIGN_EXTEND_INREG: {
     EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
     Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
     break;
Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
                                          RTLIB::LROUND_PPCF128));
     break;
   case ISD::LLROUND:
     Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
                                          RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
                                          RTLIB::LLROUND_F128,
                                          RTLIB::LLROUND_PPCF128));
     break;
+  case ISD::LRINT:
+    Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
+                                         RTLIB::LRINT_F64, RTLIB::LRINT_F80,
+                                         RTLIB::LRINT_F128,
+                                         RTLIB::LRINT_PPCF128));
+    break;
+  case ISD::LLRINT:
+    Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
+                                         RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
+                                         RTLIB::LLRINT_F128,
+                                         RTLIB::LLRINT_PPCF128));
+    break;
   case ISD::VAARG:
     Results.push_back(DAG.expandVAArg(Node));
     Results.push_back(Results[0].getValue(1));
     break;
   case ISD::VACOPY:
     Results.push_back(DAG.expandVACopy(Node));
     break;
   case ISD::EXTRACT_VECTOR_ELT:

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

#endif
   case ISD::FNEG:        Res = SoftenFloatOp_FNEG(N); break;
   case ISD::FP_EXTEND:   Res = SoftenFloatOp_FP_EXTEND(N); break;
   case ISD::FP_TO_FP16:  // Same as FP_ROUND for softening purposes
   case ISD::FP_ROUND:    Res = SoftenFloatOp_FP_ROUND(N); break;
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:  Res = SoftenFloatOp_FP_TO_XINT(N); break;
   case ISD::LROUND:      Res = SoftenFloatOp_LROUND(N); break;
   case ISD::LLROUND:     Res = SoftenFloatOp_LLROUND(N); break;
+  case ISD::LRINT:       Res = SoftenFloatOp_LRINT(N); break;
+  case ISD::LLRINT:      Res = SoftenFloatOp_LLRINT(N); break;
   case ISD::SELECT:      Res = SoftenFloatOp_SELECT(N); break;
   case ISD::SELECT_CC:   Res = SoftenFloatOp_SELECT_CC(N); break;
   case ISD::SETCC:       Res = SoftenFloatOp_SETCC(N); break;
   case ISD::STORE:
     Res = SoftenFloatOp_STORE(N, OpNo);
     // Do not try to analyze or soften this node again if the value is
     // or can be held in a register. In that case, Res.getNode() should
     // be equal to N.
return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
                                            RTLIB::LLROUND_F32,
                                            RTLIB::LLROUND_F64,
                                            RTLIB::LLROUND_F80,
                                            RTLIB::LLROUND_F128,
                                            RTLIB::LLROUND_PPCF128),
                          NVT, Op, false, SDLoc(N)).first;
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatOp_LRINT(SDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+
+  SDValue Op = GetSoftenedFloat(N->getOperand(0));
+  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
+  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LRINT_F32,
+                                           RTLIB::LRINT_F64,
+                                           RTLIB::LRINT_F80,
+                                           RTLIB::LRINT_F128,
+                                           RTLIB::LRINT_PPCF128),
+                         NVT, Op, false, SDLoc(N)).first;
+}
+
+SDValue DAGTypeLegalizer::SoftenFloatOp_LLRINT(SDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+
+  SDValue Op = GetSoftenedFloat(N->getOperand(0));
+  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
+  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LLRINT_F32,
+                                           RTLIB::LLRINT_F64,
+                                           RTLIB::LLRINT_F80,
+                                           RTLIB::LLRINT_F128,
+                                           RTLIB::LLRINT_PPCF128),
+                         NVT, Op, false, SDLoc(N)).first;
+}
+
 //===----------------------------------------------------------------------===//
 //  Float Result Expansion
 //===----------------------------------------------------------------------===//
 
 /// ExpandFloatResult - This method is called when the specified result of the
 /// specified node is found to need expansion.  At this point, the node may also
 /// have invalid operands or may have other results that need promotion, we just
 /// know that (at least) one result needs expansion.
#endif
 
   case ISD::BR_CC:      Res = ExpandFloatOp_BR_CC(N); break;
   case ISD::FCOPYSIGN:  Res = ExpandFloatOp_FCOPYSIGN(N); break;
   case ISD::FP_ROUND:   Res = ExpandFloatOp_FP_ROUND(N); break;
   case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
   case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
   case ISD::LROUND:     Res = ExpandFloatOp_LROUND(N); break;
   case ISD::LLROUND:    Res = ExpandFloatOp_LLROUND(N); break;
+  case ISD::LRINT:      Res = ExpandFloatOp_LRINT(N); break;
+  case ISD::LLRINT:     Res = ExpandFloatOp_LLRINT(N); break;
   case ISD::SELECT_CC:  Res = ExpandFloatOp_SELECT_CC(N); break;
   case ISD::SETCC:      Res = ExpandFloatOp_SETCC(N); break;
   case ISD::STORE:      Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
                                                   OpNo); break;
   }
 
   // If the result is null, the sub-method took care of registering results etc.
   if (!Res.getNode()) return false;
return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
                                            RTLIB::LLROUND_F32,
                                            RTLIB::LLROUND_F64,
                                            RTLIB::LLROUND_F80,
                                            RTLIB::LLROUND_F128,
                                            RTLIB::LLROUND_PPCF128),
                          RVT, N->getOperand(0), false, SDLoc(N)).first;
 }
 
+SDValue DAGTypeLegalizer::ExpandFloatOp_LRINT(SDNode *N) {
+  EVT RVT = N->getValueType(0);
+  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
+  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LRINT_F32,
+                                           RTLIB::LRINT_F64,
+                                           RTLIB::LRINT_F80,
+                                           RTLIB::LRINT_F128,
+                                           RTLIB::LRINT_PPCF128),
+                         RVT, N->getOperand(0), false, SDLoc(N)).first;
+}
+
+SDValue DAGTypeLegalizer::ExpandFloatOp_LLRINT(SDNode *N) {
+  EVT RVT = N->getValueType(0);
+  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
+  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
+                                           RTLIB::LLRINT_F32,
+                                           RTLIB::LLRINT_F64,
+                                           RTLIB::LLRINT_F80,
+                                           RTLIB::LLRINT_F128,
+                                           RTLIB::LLRINT_PPCF128),
+                         RVT, N->getOperand(0), false, SDLoc(N)).first;
+}
+
 //===----------------------------------------------------------------------===//
 //  Float Operand Promotion
 //===----------------------------------------------------------------------===//
 //
 
 static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) {
   if (OpVT == MVT::f16) {
       return ISD::FP16_TO_FP;

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
   case ISD::CTLZ:        ExpandIntRes_CTLZ(N, Lo, Hi); break;
   case ISD::CTPOP:       ExpandIntRes_CTPOP(N, Lo, Hi); break;
   case ISD::CTTZ_ZERO_UNDEF:
   case ISD::CTTZ:        ExpandIntRes_CTTZ(N, Lo, Hi); break;
   case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
   case ISD::FP_TO_SINT:  ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
   case ISD::FP_TO_UINT:  ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
   case ISD::LLROUND:     ExpandIntRes_LLROUND(N, Lo, Hi); break;
+  case ISD::LLRINT:      ExpandIntRes_LLRINT(N, Lo, Hi); break;
   case ISD::LOAD:        ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
   case ISD::MUL:         ExpandIntRes_MUL(N, Lo, Hi); break;
   case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
   case ISD::SDIV:        ExpandIntRes_SDIV(N, Lo, Hi); break;
   case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
   case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
   case ISD::SREM:        ExpandIntRes_SREM(N, Lo, Hi); break;
   case ISD::TRUNCATE:    ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
     Op = GetPromotedFloat(Op);
 
   SDLoc dl(N);
   EVT RetVT = N->getValueType(0);
   SplitInteger(TLI.makeLibCall(DAG, LC, RetVT, Op, true/*irrelevant*/, dl).first,
                Lo, Hi);
 }
 
+void DAGTypeLegalizer::ExpandIntRes_LLRINT(SDNode *N, SDValue &Lo,
+                                            SDValue &Hi) {
+  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
+  EVT VT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
+  if (VT == MVT::f32)
+    LC = RTLIB::LLRINT_F32;
+  else if (VT == MVT::f64)
+    LC = RTLIB::LLRINT_F64;
+  else if (VT == MVT::f80)
+    LC = RTLIB::LLRINT_F80;
+  else if (VT == MVT::f128)
+    LC = RTLIB::LLRINT_F128;
+  else if (VT == MVT::ppcf128)
+    LC = RTLIB::LLRINT_PPCF128;
+  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
+
+  SDValue Op = N->getOperand(0);
+  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
+    Op = GetPromotedFloat(Op);
+
+  SDLoc dl(N);
+  EVT RetVT = N->getValueType(0);
+  SplitInteger(TLI.makeLibCall(DAG, LC, RetVT, Op, true/*irrelevant*/, dl).first,
+               Lo, Hi);
+}
+
 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
                                          SDValue &Lo, SDValue &Hi) {
   if (ISD::isNormalLoad(N)) {
     ExpandRes_NormalLoad(N, Lo, Hi);
     return;
   }
 
   assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   void ExpandIntRes_SIGN_EXTEND       (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_TRUNCATE          (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_ZERO_EXTEND       (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_FLT_ROUNDS        (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_FP_TO_SINT        (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_FP_TO_UINT        (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_LLROUND           (SDNode *N, SDValue &Lo, SDValue &Hi);
+  void ExpandIntRes_LLRINT            (SDNode *N, SDValue &Lo, SDValue &Hi);
 
   void ExpandIntRes_Logical           (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_ADDSUB            (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_ADDSUBC           (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_ADDSUBE           (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_ADDSUBCARRY       (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_BITREVERSE        (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandIntRes_BSWAP             (SDNode *N, SDValue &Lo, SDValue &Hi);
private:
   SDValue SoftenFloatOp_FABS(SDNode *N);
   SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
   SDValue SoftenFloatOp_FNEG(SDNode *N);
   SDValue SoftenFloatOp_FP_EXTEND(SDNode *N);
   SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
   SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
   SDValue SoftenFloatOp_LROUND(SDNode *N);
   SDValue SoftenFloatOp_LLROUND(SDNode *N);
+  SDValue SoftenFloatOp_LRINT(SDNode *N);
+  SDValue SoftenFloatOp_LLRINT(SDNode *N);
   SDValue SoftenFloatOp_SELECT(SDNode *N);
   SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
   SDValue SoftenFloatOp_SETCC(SDNode *N);
   SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
 
   //===--------------------------------------------------------------------===//
   // Float Expansion Support: LegalizeFloatTypes.cpp
   //===--------------------------------------------------------------------===//
private:
   bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
   SDValue ExpandFloatOp_BR_CC(SDNode *N);
   SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
   SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
   SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
   SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
   SDValue ExpandFloatOp_LROUND(SDNode *N);
   SDValue ExpandFloatOp_LLROUND(SDNode *N);
+  SDValue ExpandFloatOp_LRINT(SDNode *N);
+  SDValue ExpandFloatOp_LLRINT(SDNode *N);
   SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
   SDValue ExpandFloatOp_SETCC(SDNode *N);
   SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
 
   void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
                                 ISD::CondCode &CCCode, const SDLoc &dl);
 
   //===--------------------------------------------------------------------===//

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::canonicalize: {
     }
 
     setValue(&I, DAG.getNode(Opcode, sdl,
                              getValue(I.getArgOperand(0)).getValueType(),
                              getValue(I.getArgOperand(0))));
     return;
   }
   case Intrinsic::lround:
-  case Intrinsic::llround: {
+  case Intrinsic::llround:
+  case Intrinsic::lrint:
+  case Intrinsic::llrint: {
     unsigned Opcode;
     switch (Intrinsic) {
     default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
     case Intrinsic::lround:  Opcode = ISD::LROUND;  break;
     case Intrinsic::llround: Opcode = ISD::LLROUND; break;
+    case Intrinsic::lrint:   Opcode = ISD::LRINT;   break;
+    case Intrinsic::llrint:  Opcode = ISD::LLRINT;  break;
     }
 
     EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
     setValue(&I, DAG.getNode(Opcode, sdl, RetVT,
                              getValue(I.getArgOperand(0))));
     return;
   }
   case Intrinsic::minnum: {

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

#endif
   case ISD::FP_TO_SINT:                 return "fp_to_sint";
   case ISD::FP_TO_UINT:                 return "fp_to_uint";
   case ISD::BITCAST:                    return "bitcast";
   case ISD::ADDRSPACECAST:              return "addrspacecast";
   case ISD::FP16_TO_FP:                 return "fp16_to_fp";
   case ISD::FP_TO_FP16:                 return "fp_to_fp16";
   case ISD::LROUND:                     return "lround";
   case ISD::LLROUND:                    return "llround";
+  case ISD::LRINT:                      return "lrint";
+  case ISD::LLRINT:                     return "llrint";
 
     // Control flow instructions
   case ISD::BR:                         return "br";
   case ISD::BRIND:                      return "brind";
   case ISD::BR_JT:                      return "br_jt";
   case ISD::BRCOND:                     return "brcond";
   case ISD::BR_CC:                      return "br_cc";
   case ISD::CALLSEQ_START:              return "callseq_start";

llvm/lib/CodeGen/TargetLoweringBase.cpp

for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
     setOperationAction(ISD::FFLOOR,     VT, Expand);
     setOperationAction(ISD::FNEARBYINT, VT, Expand);
     setOperationAction(ISD::FCEIL,      VT, Expand);
     setOperationAction(ISD::FRINT,      VT, Expand);
     setOperationAction(ISD::FTRUNC,     VT, Expand);
     setOperationAction(ISD::FROUND,     VT, Expand);
     setOperationAction(ISD::LROUND,     VT, Expand);
     setOperationAction(ISD::LLROUND,    VT, Expand);
+    setOperationAction(ISD::LRINT,      VT, Expand);
+    setOperationAction(ISD::LLRINT,     VT, Expand);
   }
 
   // Default ISD::TRAP to expand (which turns it into abort).
   setOperationAction(ISD::TRAP, MVT::Other, Expand);
 
   // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
   // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
   setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);

llvm/lib/IR/Verifier.cpp

case Intrinsic::umul_fix: {
     } else {
       Assert(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(),
              "the scale of umul_fix must be less than or equal to the width of "
              "the operands");
     }
     break;
   }
   case Intrinsic::lround:
-  case Intrinsic::llround: {
+  case Intrinsic::llround:
+  case Intrinsic::lrint:
+  case Intrinsic::llrint: {
     Type *ValTy = Call.getArgOperand(0)->getType();
     Type *ResultTy = Call.getType();
     Assert(!ValTy->isVectorTy() && !ResultTy->isVectorTy(),
            "Intrinsic does not support vectors", &Call);
     break;
   }
   };
 }

llvm/lib/Target/X86/X86ISelLowering.cpp

if (UseX87) {
     setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
     setOperationAction(ISD::FCEIL,  MVT::f80, Expand);
     setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
     setOperationAction(ISD::FRINT,  MVT::f80, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
     setOperationAction(ISD::FMA, MVT::f80, Expand);
     setOperationAction(ISD::LROUND, MVT::f80, Expand);
     setOperationAction(ISD::LLROUND, MVT::f80, Expand);
+    setOperationAction(ISD::LRINT, MVT::f80, Expand);
+    setOperationAction(ISD::LLRINT, MVT::f80, Expand);
   }
 
   // Always use a library call for pow.
   setOperationAction(ISD::FPOW             , MVT::f32  , Expand);
   setOperationAction(ISD::FPOW             , MVT::f64  , Expand);
   setOperationAction(ISD::FPOW             , MVT::f80  , Expand);
 
   setOperationAction(ISD::FLOG, MVT::f80, Expand);

llvm/test/CodeGen/AArch64/llrint-conv.ll

+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsws:
+; CHECK:       bl      llrintf
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       b       llrintf
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       bl      llrint
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       b       llrint
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswl:
+; CHECK:       bl      llrintl
+define i32 @testmswl(fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f128(fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsll:
+; CHECK:       b       llrintl
+define i64 @testmsll(fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f128(fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone
+declare i64 @llvm.llrint.f128(fp128) nounwind readnone

llvm/test/CodeGen/AArch64/lrint-conv.ll

+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsws:
+; CHECK:       bl      lrintf
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       b       lrintf
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       bl      lrint
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       b       lrint
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswl:
+; CHECK:       bl      lrintl
+define dso_local i32 @testmswl(fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsll:
+; CHECK:       b       lrintl
+define dso_local i64 @testmsll(fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
+declare i64 @llvm.lrint.i64.f128(fp128) nounwind readnone

llvm/test/CodeGen/ARM/llrint-conv.ll

+; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
+; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
+
+; SOFTFP-LABEL: testmsxs_builtin:
+; SOFTFP:       bl      llrintf
+; HARDFP-LABEL: testmsxs_builtin:
+; HARDFP:       bl      llrintf
+define i64 @testmsxs_builtin(float %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+; SOFTFP-LABEL: testmsxd_builtin:
+; SOFTFP:       bl      llrint
+; HARDFP-LABEL: testmsxd_builtin:
+; HARDFP:       bl      llrint
+define i64 @testmsxd_builtin(double %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone

llvm/test/CodeGen/ARM/lrint-conv.ll

+; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
+; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
+
+; SOFTFP-LABEL: testmsws_builtin:
+; SOFTFP:       bl      lrintf
+; HARDFP-LABEL: testmsws_builtin:
+; HARDFP:       bl      lrintf
+define i32 @testmsws_builtin(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  ret i32 %0
+}
+
+; SOFTFP-LABEL: testmswd_builtin:
+; SOFTFP:       bl      lrint
+; HARDFP-LABEL: testmswd_builtin:
+; HARDFP:       bl      lrint
+define i32 @testmswd_builtin(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
+declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

llvm/test/CodeGen/Mips/llrint-conv.ll

+; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
+
+define signext i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK:       jal     llrintf
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK:       jal     llrintf
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+define signext i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK:       jal     llrint
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK:       jal     llrint
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+define signext i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK:       jal     llrintl
+entry:
+  %0 = tail call i64 @llvm.llrint.f128(fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK:       jal     llrintl
+entry:
+  %0 = tail call i64 @llvm.llrint.f128(fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone
+declare i64 @llvm.llrint.f128(fp128) nounwind readnone

llvm/test/CodeGen/Mips/lrint-conv.ll

+; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
+
+define signext i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK:       jal     lrintf
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK:       jal     lrintf
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  ret i64 %0
+}
+
+define signext i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK:       jal     lrint
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK:       jal     lrint
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  ret i64 %0
+}
+
+define signext i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK:       jal     lrintl
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define signext i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK:       jal     lrintl
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
+declare i64 @llvm.lrint.i64.f128(fp128) nounwind readnone

llvm/test/CodeGen/PowerPC/llrint-conv.ll

+; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s
+
+; CHECK-LABEL: testmsws:
+; CHECK:       bl      llrintf
+define signext i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       bl      llrintf
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       bl      llrint
+define signext i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       bl      llrint
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswl:
+; CHECK:       bl      llrintl
+define signext i32 @testmswl(ppc_fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.ppcf128(ppc_fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsll:
+; CHECK:       bl      llrintl
+define i64 @testmsll(ppc_fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.llrint.ppcf128(ppc_fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone
+declare i64 @llvm.llrint.ppcf128(ppc_fp128) nounwind readnone

llvm/test/CodeGen/PowerPC/lrint-conv.ll

+; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s
+
+; CHECK-LABEL: testmsws:
+; CHECK:       bl      lrintf
+define signext i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       bl      lrintf
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       bl      lrint
+define signext i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       bl      lrint
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  ret i64 %0
+}
+
+; CHECK-LABEL: testmswl:
+; CHECK:       bl      lrintl
+define signext i32 @testmswl(ppc_fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.ppcf128(ppc_fp128 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmsll:
+; CHECK:       bl      lrintl
+define i64 @testmsll(ppc_fp128 %x) {
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.ppcf128(ppc_fp128 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
+declare i64 @llvm.lrint.i64.ppcf128(ppc_fp128) nounwind readnone

llvm/test/CodeGen/X86/llrint-conv-i32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown             | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+
+define i64 @testmsxs_builtin(float %x) {
+; CHECK-LABEL: testmsxs_builtin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fstps (%esp)
+; CHECK-NEXT:    calll llrintf
+; CHECK-NEXT:    popl %ecx
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+;
+; SSE2-LABEL: testmsxs_builtin:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    pushl %eax
+; SSE2-NEXT:    .cfi_def_cfa_offset 8
+; SSE2-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    movss %xmm0, (%esp)
+; SSE2-NEXT:    calll llrintf
+; SSE2-NEXT:    popl %ecx
+; SSE2-NEXT:    .cfi_def_cfa_offset 4
+; SSE2-NEXT:    retl
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+define i64 @testmsxd_builtin(double %x) {
+; CHECK-LABEL: testmsxd_builtin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fstpl (%esp)
+; CHECK-NEXT:    calll llrint
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+;
+; SSE2-LABEL: testmsxd_builtin:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    subl $8, %esp
+; SSE2-NEXT:    .cfi_def_cfa_offset 12
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT:    movsd %xmm0, (%esp)
+; SSE2-NEXT:    calll llrint
+; SSE2-NEXT:    addl $8, %esp
+; SSE2-NEXT:    .cfi_def_cfa_offset 4
+; SSE2-NEXT:    retl
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone

llvm/test/CodeGen/X86/llrint-conv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq llrintf
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp llrintf # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.llrint.f32(float %x)
+  ret i64 %0
+}
+
+define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq llrint
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp llrint # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.llrint.f64(double %x)
+  ret i64 %0
+}
+
+define dso_local i32 @testmswl(x86_fp80 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq $24, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fstpt (%rsp)
+; CHECK-NEXT:    callq llrintl
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.llrint.f80(x86_fp80 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define dso_local i64 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp llrintl # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.llrint.f80(x86_fp80 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llrint.f32(float) nounwind readnone
+declare i64 @llvm.llrint.f64(double) nounwind readnone
+declare i64 @llvm.llrint.f80(x86_fp80) nounwind readnone

llvm/test/CodeGen/X86/lrint-conv-i32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown             | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+
+define i32 @testmsws_builtin(float %x) {
+; CHECK-LABEL: testmsws_builtin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp lrintf # TAILCALL
+;
+; SSE2-LABEL: testmsws_builtin:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    jmp lrintf # TAILCALL
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  ret i32 %0
+}
+
+define i32 @testmswd_builtin(double %x) {
+; CHECK-LABEL: testmswd_builtin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp lrint # TAILCALL
+;
+; SSE2-LABEL: testmswd_builtin:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    jmp lrint # TAILCALL
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
+declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

llvm/test/CodeGen/X86/lrint-conv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq lrintf
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp lrintf # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+  ret i64 %0
+}
+
+define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq lrint
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp lrint # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+  ret i64 %0
+}
+
+define dso_local i32 @testmswl(x86_fp80 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subq $24, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fstpt (%rsp)
+; CHECK-NEXT:    callq lrintl
+; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+define dso_local i64 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    jmp lrintl # TAILCALL
+entry:
+  %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
+declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone