- User Since
- Sep 5 2014, 5:55 AM (232 w, 3 d)
Wed, Jan 30
Update based on off-list feedback:
- Added a section on allowed operations to clarify this is a first class type.
- Remove initial proposal on the flag for not inheriting vlen; there's more pushback against allowing runtime multiple changes. I think this design could still be extended to support that in the future, but I'm afraid I'll have to leave that battle to the RVV team.
- Minor wording changes.
Nov 2 2018
- Unified ScalableSize representation
- Changed to uint64_t + boolean, since we no longer allow scalable vectors in aggregates
- Removed aggregate and mixed unit tests
- Added checks in verifier to prevent scalable vectors being included in structs or arrays
- Changed lookup to use ElementCount
- Moved ElementCount to a new file
- More unit tests
Updated based on feedback:
- Add reasons for restrictions on global/aggregates
- Change size query struct to an integer + a boolean instead of two integers.
Oct 31 2018
Oct 25 2018
Updated based on discussions at the 2018 devmeeting
Oct 24 2018
Abandoning this. At the devmeeting it was agreed that 'getPrimitiveSizeInBits' should continue to work as-is for fixed-length vectors and only behave differently for scalable vectors.
Oct 11 2018
Sep 4 2018
Aug 1 2018
Jul 26 2018
Jul 19 2018
Jul 16 2018
Indeed, we shouldn't allow scalable vectors to be globals. I've added a check for that in the verifier, plus unit tests and a small update to the langref. Thanks.
Jul 12 2018
I think the discussion on the mailing list has reached agreement on this type being suitable for both SVE and RVV; any review comments on the code or tests?
Jun 7 2018
Fixed string representation of scalable vectors which don't map to the existing defined set of MVTs.
Jun 6 2018
Removed unnecessary metadata.
Jun 5 2018
Updated RFC including a list of patches for simple codegen using this extension has been posted: http://lists.llvm.org/pipermail/llvm-dev/2018-June/123780.html
Nov 1 2017
I have also changed vscale and stepvector to be intrinsics, but as that makes those patches just an addition to Intrinsics.td I won't post them yet.
Changed textual IR format to match Chris's suggestion from the mailing list.
Oct 3 2017
Aug 2 2017
Jun 1 2017
New RFC posted to llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2017-June/113587.html
May 3 2017
May 2 2017
Improved constructor based on Renato's suggestion. Thanks.
Apr 26 2017
Apr 20 2017
Added unit tests via gtest framework.
Changed getHalfNumVectorElementsVT to use 'EltCnt.Min' when determining whether the current vector length is evenly divisible.
Changed iterator names to be more obvious.
Apr 19 2017
Changed 'Min' to unsigned.
Moved text to asserts instead of comments.
Added FIXME to explain why extended scalable vector types aren't handled yet.
Changed SimpleValueType enum back to 8 bits, but made it unsigned. Renumbered all of them, with 0 now being the invalid value.
Removed unused functions, moved assert on halving the number of elements when there's an odd element count.
Apr 18 2017
Apr 13 2017
See http://lists.llvm.org/pipermail/llvm-dev/2017-March/110772.html for earlier discussion on these types.
Apr 11 2017
Apr 3 2017
Changed to transform combined constructs to simd in ParseOpenMP.cpp instead of creating a new pragma handler. This also made it easier to add support for 'declare simd': only needed the addition of a check for the option when code generating functions to enable it, so I've added a RUN line to test it in the 'declare simd' codegen tests.
Mar 29 2017
Mar 28 2017
Feb 6 2017
For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.