[ARM] Adjust calling conventions for MVE vectors.

[simon_tatham]

Summary

This allows the full set of MVE-relevant vector types to be passed as
arguments in vector registers.

[ostannard]

Why do we need to treat this differently to NEON? As far as I know the calling convention is the same.

Can this be tested now, or does it need the next patch? In either case, some tests should be added somewhere.

[simon_tatham]

The problem with the existing NEON calling convention code was that it started by pretending all 128-bit vectors are v2f64. But that's the one vector type MVE doesn't have any support for, so there were lots of annoying ISel errors.

Even so, I think you're right that this was the wrong solution. I've managed to get all the tests passing without modifying ARMCallingConv.td at all, by the alternative technique of making v2f64 a legal type in MVE-land even though no actual instructions will usefully operate on one (i.e. everything other than loads and stores are set to Expand). I can fold those changes into other patches in this series, so I think this one can be abandoned.

[dmgreen]

Hello. I'm a little worried about the implication of making v2f64 legal, from a codegen point of view. My understanding is that that would make a lot of cost calculations wrong at least? And by default the vectoriser would start very happily making v2f64 vectors, which we would have trouble dealing with. I may be mistaken about the ramifications of doing it, but if we were to mark v2f64 as legal just for calling conventions, and it did then hurt us in a lot of other places, that seems like a poor tradeoff to me.

[simon_tatham]

I think that's unlikely to be too much of a problem, because it exactly mimics the state of affairs for AArch32 NEON, which also does not support arithmetic operations on vectors of two f64s. The existing NEON setup code in ARMISelLowering.cpp makes v2f64 a legal type for argument passing purposes but sets most operations to Expand, and my revised version of D60708 (which I seem not to have uploaded yet, oops) just modifies an existing if statement or two so that exactly the same handling applies to MVE.

[simon_tatham]

I just spotted this old patch in a list of my unclosed reviews. v2f64 is now legal in MVE by other means, so this patch is so far out of date that it would have to be done all over again if we needed it. Garbage-collecting it.

llvm/lib/Target/ARM/ARMCallingConv.cpp

static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT,
   case MVT::f16:
   case MVT::f32:
     RegList = SRegList;
     break;
   case MVT::v4f16:
   case MVT::f64:
     RegList = DRegList;
     break;
+  case MVT::v4i32:
+  case MVT::v4f32:
+    // TODO: assert this is mve
   case MVT::v8f16:
+  case MVT::v2i64:
   case MVT::v2f64:
     RegList = QRegList;
     break;
   default:
     llvm_unreachable("Unexpected member type for block aggregate");
     break;
   }
 

llvm/lib/Target/ARM/ARMCallingConv.td

 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 // This describes the calling conventions for ARM architecture.
 //===----------------------------------------------------------------------===//
 
+/// CCIfSubtarget - Match if the current subtarget has a feature F.
+class CCIfSubtarget<string F, CCAction A>
+    : CCIf<!strconcat("static_cast<const ARMSubtarget&>"
+                       "(State.getMachineFunction().getSubtarget()).",
+                     F),
+          A>;
+
+class CCIfNotSubtarget<string F, CCAction A>
+    : CCIf<!strconcat("!static_cast<const ARMSubtarget&>"
+                       "(State.getMachineFunction().getSubtarget()).",
+                     F),
+          A>;
+
 /// CCIfAlign - Match of the original alignment of the arg
 class CCIfAlign<string Align, CCAction A>:
   CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
 
 //===----------------------------------------------------------------------===//
 // ARM APCS Calling Convention
 //===----------------------------------------------------------------------===//
 let Entry = 1 in
 def CC_ARM_APCS : CallingConv<[
 
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
     
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64, v8i16, v16i8, v4f32],
+                CCBitConvertToType<v4i32>>>,
 
   // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
   CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
 
   CCIfType<[f32], CCBitConvertToType<i32>>,
   CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
 
   CCIfType<[i32], CCAssignToStack<4, 4>>,
   CCIfType<[f64], CCAssignToStack<8, 4>>,
-  CCIfType<[v2f64], CCAssignToStack<16, 4>>
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2f64], CCAssignToStack<16, 4>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()",
+                CCIfType<[v4i32], CCAssignToStack<16, 4>>>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_APCS : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64, v8i16, v16i8, v4f32],
+                CCBitConvertToType<v4i32>>>,
 
   CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
 
   CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
   CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
 //===----------------------------------------------------------------------===//
 let Entry = 1 in
 def FastCC_ARM_APCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64, v8i16, v16i8, v4f32],
+                CCBitConvertToType<v4i32>>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
 
   // CPRCs may be allocated to co-processor registers or the stack - they
   // may never be allocated to core registers. 
   CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
-  CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2f64],
+                   CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32],
+                   CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>>,
 
   CCDelegateTo<CC_ARM_APCS>
 ]>;
 
 let Entry = 1 in
 def RetFastCC_ARM_APCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64, v8i16, v16i8, v4f32],
+                CCBitConvertToType<v4i32>>>,
+
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()",
+                CCIfType<[v4i32], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
 
-  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
   CCDelegateTo<RetCC_ARM_APCS>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM APCS Calling Convention for GHC
 //===----------------------------------------------------------------------===//
 
 let Entry = 1 in
 def CC_ARM_APCS_GHC : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64, v8i16, v16i8, v4f32],
+                CCBitConvertToType<v4i32>>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
   CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
   CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
 
   // Promote i8/i16 arguments to i32.
   CCIfType<[i8, i16], CCPromoteToType<i32>>,
 
def CC_ARM_AAPCS_Common : CallingConv<[
   CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
   CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
                        CCAssignToReg<[R0, R1, R2, R3]>>>,
 
   CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
   CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
   CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
-  CCIfType<[v2f64], CCIfAlign<"16",
-           CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
-  CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
+
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2f64], CCIfAlign<"16",
+                   CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2f64],
+                   CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>>,
+
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64], CCIfAlign<"16",
+                    CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64],
+                   CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>>,
+
+
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4f32], CCIfAlign<"16",
+                CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4f32],
+                CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>>,
+
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32], CCIfAlign<"16",
+                 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32],
+                CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>>
 ]>;
 
 def RetCC_ARM_AAPCS_Common : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
   CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
   CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM AAPCS (EABI) Calling Convention
 //===----------------------------------------------------------------------===//
 
 let Entry = 1 in
 def CC_ARM_AAPCS : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
   // The 'nest' parameter, if any, is passed in R12.
   CCIfNest<CCAssignToReg<[R12]>>,
 
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()",
+                CCIfType<[v2i64, v8i16, v8f16, v16i8, v4f32],
+                 CCBitConvertToType<v4i32>>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
   CCDelegateTo<CC_ARM_AAPCS_Common>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_AAPCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()",
+                   CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32],
+                    CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()",
+                 CCIfType<[v2i64, v8i16, v8f16, v16i8, v4f32],
+                  CCBitConvertToType<v4i32>>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,

 
 let Entry = 1 in
 def CC_ARM_AAPCS_VFP : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32, v8i16, v16i8],
+                   CCBitConvertToType<v2i64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v8i16, v16i8],
+                CCBitConvertToType<v4i32>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v8f16, v4f32],
+                   CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v8f16],
+                CCBitConvertToType<v4f32>>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // HFAs are passed in a contiguous block of registers, or on the stack
   CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
 
-  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4f32], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
   CCDelegateTo<CC_ARM_AAPCS_Common>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_AAPCS_VFP : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32, v8i16, v16i8],
+                   CCBitConvertToType<v2i64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v8i16, v16i8],
+                CCBitConvertToType<v4i32>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v8f16, v4f32],
+                CCBitConvertToType<v2f64>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v8f16],
+                CCBitConvertToType<v4f32>>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
-  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+  CCIfNotSubtarget<"hasMVEIntegerOps()", CCIfType<[v2i64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4f32], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+  CCIfSubtarget<"hasMVEIntegerOps()", CCIfType<[v4i32], CCAssignToReg<[Q0, Q1, Q2, Q3]>>>,
+
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                       S9, S10, S11, S12, S13, S14, S15]>>,
   CCDelegateTo<RetCC_ARM_AAPCS_Common>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Callee-saved register lists.
 //===----------------------------------------------------------------------===//
 
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+// TODO: Do we need to update this for MVE with only d0-d15?
 def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
 
 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
                                      (sequence "D%u", 15, 8))>;
 
 // R8 is used to pass swifterror, remove it from CSR.
 def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
 

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (VA.isRegLoc()) {
 
 
         if (RegVT == MVT::f16)
           RC = &ARM::HPRRegClass;
         else if (RegVT == MVT::f32)
           RC = &ARM::SPRRegClass;
         else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
           RC = &ARM::DPRRegClass;
-        else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
+        else if (RegVT == MVT::v4f32 || RegVT == MVT::v8f16 ||
+                 RegVT == MVT::v2i64 || RegVT == MVT::v4i32 ||
+                 RegVT == MVT::v8i16 || RegVT == MVT::v16i8)
+          RC = &ARM::QPRRegClass;
+        else if (RegVT == MVT::v2f64 && Subtarget->hasNEON())
           RC = &ARM::QPRRegClass;
         else if (RegVT == MVT::i32)
           RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
                                            : &ARM::GPRRegClass;
         else
           llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
 
         // Transform the arguments in physical registers into virtual ones.