[RISCV] Expand function call to "call" pseudoinstruction

[shiva0217]

Summary

To do this:

1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol.
2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol.
3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol.

[apazos]

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

49

maybe change leave relocation types -> preserve relocation types, to be in line with the term you use in other patches.

lib/Target/RISCV/RISCVAsmPrinter.cpp

83

NULL->nullptr

116

I think creating the instruction with RISCV::X1 would be clearer than referencing the alternative return address name.

[shiva0217]

Update patch to address Ana's comments.

[mgrang]

lib/Target/RISCV/RISCVAsmPrinter.cpp

116

Although it is cleaner to create the instruction with RISCV::X1 specified explicitly, it prevents PseudoTailCall from re-using this function. PseudoTailCall is still a call but does not use X1.

@shiva0217 Could you please restore the use of "unsigned Ra" to reference the return address name?

[shiva0217]

Update the patch to address @mgrang's comments.

[asb]

Thanks for this as always Shiva. Mostly minor comments or questions in this review.

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

26

Maybe be more explicit, e.g. "Return true if the relocation should be with a symbol rather than section".

29

Is this universally true, or true only for ELF::R_RISCV_PCREL_LO12_I?

lib/Target/RISCV/RISCVAsmPrinter.cpp

79

It would be good to have a comment explaining that a function call will be expanded to auipc+jalr, both with relocations.

108

AUPIC -> AUIPC

lib/Target/RISCV/RISCVISelLowering.cpp

993

"can be matched by"

994–1000

Might as well just use dyn_cast in the if conditions here.

lib/Target/RISCV/RISCVInstrInfo.td

144–168

Maybe it's better to have def simm21_lsb0 : Operand<XLenVT> { and a def br_target : Operand<OtherVT> {.

[shiva0217]

Update patch to address Alex's comments.

[shiva0217]

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

29

It seems that gcc always emit relocations with symbols which could observe by readelf object files. So it's probably universally true. I changed the comment as "Return true to preserve symbol with relocations instead of section plus offset". Is it ok?

[asb]

Thanks Shiva. This looks good to me - just two additional minor suggestions prior to commit (add a TODO comment and switch to using dyn_cast in one place).

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

29

That seems very conservative. It's probably the right starting point, but maybe a TODO comment would be worthwhile. .g. 'TODO: this is very conservative, update once RISC-V psABI requirements are clarified'. Although the current binutils linker seems to have many limitations, wouldn't we expect that needsRelocateWithSymbol can be false in general as long as relaxation is disabled?

Returning true unconditionally seems sensible for now, but lets leave a note to come back to this.

lib/Target/RISCV/RISCVISelLowering.cpp

994–995

Can use dyn_cast here too

[shiva0217]

Update the patch to emit pseudo call in the assembly as Alex's comments in https://reviews.llvm.org/D44886#inline-398646.

[shiva0217]

Fix typo in comments.

[shiva0217]

Hi Alex. I have changed the patch to generate call pesudoinstruciton. Do you think the updated is ok?

[asb]

Hi Shiva. Thanks for this, I think the best way of landing this is to split the MC and codegen changes. Could you please:

• Make a new review that contains only the changes required to support call foo in the MC layer
• Rebase this patch on top of that, and update the title to something like 'Expand function call to "call" pseudoinstruction'

[shiva0217]

Update patch to address Alex's comments.

[efriedma]

Why do we want to do this? As far as I can tell, it leads to worse code (e.g. br_fcmp_store_load_stack_slot materializes the address of @dummy twice).

[efriedma]

Oh, nevermind, missed the part about linker relaxation. Please add a comment to the code which mentions that.

[shiva0217]

Update patch to address Eli's comments.

[asb]

Thanks Shiva. I think just two outstanding issues. Some of the test files in test/CodeGen/RISCV that weren't generated with update_llc_test_checks.py have unwanted changes in this patch. With that fixed, this is looking good to me.

lib/Target/RISCV/RISCVInstrInfo.td

634–643

I'd change the second sentence to "This is desirable, as an auipc+jalr pair with R_RISCV_CALL and R_RISCV_RELAX relocations can be be relaxed by the linker if the offset fits in a signed 21-bit immediate."

[shiva0217]

Update patch to address Alex's comments.

[mgrang]

@shiva0217 Could you please rebase and commit this patch? My tail call patch D45395 depends on this patch.

[shiva0217]

In D44885#1077561, @mgrang wrote:

@shiva0217 Could you please rebase and commit this patch? My tail call patch D45395 depends on this patch?

Hi @mgrang, I'll update the patches in the next few hours.

[shiva0217]

Rebase the patch due the updated on https://reviews.llvm.org/D45859.

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

public:
 
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved) const override;
 
   std::unique_ptr<MCObjectWriter>
   createObjectWriter(raw_pwrite_stream &OS) const override;
 
+  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+                             const MCValue &Target) override {
+    const unsigned FixupKind = Fixup.getKind();
+    // It's hard to fix fixup_riscv_pcrel_lo12_i by assembler, so we preserve
+    // relocation types and let linker to resolve it.
+    //
+    //.LtmpX:
+    //      auipc  ra, %pcrel_hi(foo)
+    //      jalr   ra, ra, %pcrel_lo(.LtmpX)
+    //
+    // For R_RISCV_PCREL_LO12_I, linker will
+    // 1. Find high part instruction(auipc) by .LtmpX
+    // 2. Find symbol(foo) in auipc's relocation type
+    // 3. Resolve offset by symbol(foo)
+    if (FixupKind == RISCV::fixup_riscv_pcrel_lo12_i ||
+        FixupKind == RISCV::fixup_riscv_pcrel_hi20)
+      return true;
+    return false;
+  }
+
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   unsigned getNumFixupKinds() const override {
     return RISCV::NumTargetFixupKinds;
   }
 

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

 
 namespace {
 class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
 
   ~RISCVELFObjectWriter() override;
 
+  // Return true to preserve symbol with relocations instead of section
+  // plus offset.
+  bool needsRelocateWithSymbol(const MCSymbol &Sym,
+                               unsigned Type) const override {
+    return true;
+  }
+
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
                         const MCFixup &Fixup, bool IsPCRel) const override;
 };
 }
 
 RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
     : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,

lib/Target/RISCV/RISCVAsmPrinter.cpp

 #include "RISCVTargetMachine.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
public:
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              unsigned AsmVariant, const char *ExtraCode,
                              raw_ostream &OS) override;
 
   void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
+  void expandFunctionCall(const MachineInstr *MI);
+
   // Wrapper needed for tblgenned pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
     return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
   }
 };
 }
 
 #define GEN_COMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
                           OutStreamer->getContext());
   AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
 }
 
 // Simple pseudo-instructions have their lowering (with expansion to real
 // instructions) auto-generated.
 #include "RISCVGenMCPseudoLowering.inc"
 
+// Expand PseudoCALL to AUIPC and JALR with relocation types.
+void RISCVAsmPrinter::expandFunctionCall(const MachineInstr *MI) {
+  MCInst TmpInst;
+  MachineOperand Func = MI->getOperand(0);
+  MCSymbol *Sym = nullptr;
+  unsigned Ra = RISCV::X1;
+
+  assert(Func.isGlobal() || Func.isSymbol());
+
+  if (Func.isGlobal())
+    Sym = getSymbol(Func.getGlobal());
+  else if (Func.isSymbol())
+    Sym = GetExternalSymbolSymbol(Func.getSymbolName());
+
+  const MCExpr *Expr;
+
+  // Create high part expression HiExpr for AUIPC.
+  Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, OutContext);
+  const MCExpr *HiExpr =
+    RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_PCREL_HI, OutContext);
+
+  // Create low part expression LoExpr for JALR.
+  auto HiLabel = OutContext.createTempSymbol();
+  Expr = MCSymbolRefExpr::create(HiLabel, MCSymbolRefExpr::VK_None, OutContext);
+  const MCExpr *LoExpr =
+    RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_PCREL_LO, OutContext);
+
+  // Emit .LtmpX:
+  OutStreamer->EmitLabel(HiLabel);
+
+  // Emit AUIPC Ra, %pcrel_hi(Func)
+  TmpInst = MCInstBuilder(RISCV::AUIPC)
+              .addReg(Ra)
+              .addOperand(MCOperand::createExpr(HiExpr));
+  EmitToStreamer(*OutStreamer, TmpInst);
+
+  // Emit JALR Ra, Ra, %pcrel_lo(.LtmpX)
+  TmpInst = MCInstBuilder(RISCV::JALR)
+              .addReg(Ra)
+              .addReg(Ra)
+              .addOperand(MCOperand::createExpr(LoExpr));
+  EmitToStreamer(*OutStreamer, TmpInst);
+}
+
 void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   // Do any auto-generated pseudo lowerings.
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
+  if (MI->getOpcode() == RISCV::PseudoCALL)
+    return expandFunctionCall(MI);
+
   MCInst TmpInst;
   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
   EmitToStreamer(*OutStreamer, TmpInst);
 }
 
 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                       unsigned AsmVariant,
                                       const char *ExtraCode, raw_ostream &OS) {

lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   SDValue Glue;
 
   // Build a sequence of copy-to-reg nodes, chained and glued together.
   for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
+  // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
+  // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
+  // split it and then direct call can be matched by PseudoCALL.
   if (isa<GlobalAddressSDNode>(Callee)) {
-    Callee = lowerGlobalAddress(Callee, DAG);
-  } else if (isa<ExternalSymbolSDNode>(Callee)) {
-    Callee = lowerExternalSymbol(Callee, DAG);
+    auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
+    Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
+  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
+    const char *Sym = S->getSymbol();
+    Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
   }
 
   // The first call operand is the chain and the second is the target address.
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are
   // known live into the call.

lib/Target/RISCV/RISCVInstrInfo.cpp

unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
 
   switch (Opcode) {
   default: { return get(Opcode).getSize(); }
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
     return 0;
+  case RISCV::PseudoCALL:
+    return 8;
   case TargetOpcode::INLINEASM: {
     const MachineFunction &MF = *MI.getParent()->getParent();
     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
                               *TM.getMCAsmInfo());
   }
   }
 }

lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isUInt<20>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 // A 21-bit signed immediate where the least significant bit is zero.
-def simm21_lsb0 : Operand<OtherVT> {
+def simm21_lsb0 : Operand<XLenVT> {
+  let ParserMatchClass = SImmAsmOperand<21, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (MCOp.evaluateAsConstantImm(Imm))
+      return isShiftedInt<20, 1>(Imm);
+    return MCOp.isBareSymbolRef();
+  }];
+}
+
+def br_target : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<21, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isShiftedInt<20, 1>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 // A parameterized register class alternative to i32imm/i64imm from Target.td.
 def ixlenimm : Operand<XLenVT>;
 
 // Standalone (codegen-only) immleaf patterns.
 def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
 
 // Addressing modes.
 // Necessary because a frameindex can't be matched directly in a pattern.
 def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;

 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20:$imm20),
                   "lui", "$rd, $imm20">;
 
 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20:$imm20),
                     "auipc", "$rd, $imm20">;
 
 let isCall = 1 in
-def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0:$imm20),
+def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins br_target:$imm20),
                   "jal", "$rd, $imm20">;
 
 let isCall = 1 in
 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
                    (ins GPR:$rs1, simm12:$imm12),
                    "jalr", "$rd, $rs1, $imm12">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 

 def : InstAlias<"ble $rs, $rt, $offset",
                 (BGE  GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
 def : InstAlias<"bgtu $rs, $rt, $offset",
                 (BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
 def : InstAlias<"bleu $rs, $rt, $offset",
                 (BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
 
 // "ret" has more weight since "ret" and "jr" alias the same "jalr" instruction.
-def : InstAlias<"j $offset",   (JAL  X0, simm21_lsb0:$offset)>;
-def : InstAlias<"jal $offset", (JAL  X1, simm21_lsb0:$offset)>;
+def : InstAlias<"j $offset",   (JAL  X0, br_target:$offset)>;
+def : InstAlias<"jal $offset", (JAL  X1, br_target:$offset)>;
 def : InstAlias<"jr $rs",      (JALR X0, GPR:$rs, 0)>;
 def : InstAlias<"jalr $rs",    (JALR X1, GPR:$rs, 0)>;
 def : InstAlias<"ret",         (JALR X0,      X1, 0), 2>;
 // TODO call
 // TODO tail
 
 def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
 

 def : BccSwapPat<setugt, BLTU>;
 def : BccSwapPat<setule, BGEU>;
 
 // An extra pattern is needed for a brcond without a setcc (i.e. where the
 // condition was calculated elsewhere).
 def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
 
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
-def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>,
-               PseudoInstExpansion<(JAL X0, simm21_lsb0:$imm20)>;
+def PseudoBR : Pseudo<(outs), (ins br_target:$imm20), [(br bb:$imm20)]>,
+               PseudoInstExpansion<(JAL X0, br_target:$imm20)>;
 
 let isCall = 1, Defs=[X1] in
 let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
 def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>,
                   PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
 
 def : Pat<(brind GPR:$rs1), (PseudoBRIND GPR:$rs1, 0)>;
 def : Pat<(brind (add GPR:$rs1, simm12:$imm12)),
           (PseudoBRIND GPR:$rs1, simm12:$imm12)>;
 
+// PseudoCALL is a pseudo instruction which will eventaully expand to auipc
+// and jalr.
+let isCall = 1, Defs = [X1] in
+def PseudoCALL : Pseudo<(outs), (ins simm21_lsb0:$func),
+                        [(Call tglobaladdr:$func)]>;
+
+def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
+
 let isCall = 1, Defs = [X1] in
-def PseudoCALL : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
+def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
                 PseudoInstExpansion<(JALR X0, X1, 0)>;
 
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, RVInst Inst> {

test/CodeGen/RISCV/alloca.ll

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    addi s0, sp, 16
 ; RV32I-NEXT:    addi a0, a0, 15
 ; RV32I-NEXT:    andi a0, a0, -16
 ; RV32I-NEXT:    sub a0, sp, a0
 ; RV32I-NEXT:    mv sp, a0
-; RV32I-NEXT:    lui a1, %hi(notdead)
-; RV32I-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    addi sp, s0, -16
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = alloca i8, i32 %n
   call void @notdead(i8* %1)
   ret void

 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    sw s1, 4(sp)
 ; RV32I-NEXT:    addi s0, sp, 16
 ; RV32I-NEXT:    mv s1, sp
 ; RV32I-NEXT:    addi a0, a0, 15
 ; RV32I-NEXT:    andi a0, a0, -16
 ; RV32I-NEXT:    sub a0, sp, a0
 ; RV32I-NEXT:    mv sp, a0
-; RV32I-NEXT:    lui a1, %hi(notdead)
-; RV32I-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    mv sp, s1
 ; RV32I-NEXT:    addi sp, s0, -16
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %sp = call i8* @llvm.stacksave()

 ; RV32I-NEXT:    addi a1, zero, 12
 ; RV32I-NEXT:    sw a1, 12(sp)
 ; RV32I-NEXT:    addi a1, zero, 11
 ; RV32I-NEXT:    sw a1, 8(sp)
 ; RV32I-NEXT:    addi a1, zero, 10
 ; RV32I-NEXT:    sw a1, 4(sp)
 ; RV32I-NEXT:    addi a1, zero, 9
 ; RV32I-NEXT:    sw a1, 0(sp)
-; RV32I-NEXT:    lui a1, %hi(func)
-; RV32I-NEXT:    addi t0, a1, %lo(func)
 ; RV32I-NEXT:    addi a1, zero, 2
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    addi a5, zero, 6
 ; RV32I-NEXT:    addi a6, zero, 7
 ; RV32I-NEXT:    addi a7, zero, 8
-; RV32I-NEXT:    jalr t0
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(func)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    addi sp, s0, -16
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = alloca i8, i32 %n
   call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8,
                   i32 9, i32 10, i32 11, i32 12)
   ret void
 }

test/CodeGen/RISCV/analyze-branch.ll

 define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
 ; RV32I-LABEL: test_bcc_fallthrough_taken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a1, zero, 42
 ; RV32I-NEXT:    bne a0, a1, .LBB0_3
 ; RV32I-NEXT:  # %bb.1: # %true
-; RV32I-NEXT:    lui a0, %hi(test_true)
-; RV32I-NEXT:    addi a0, a0, %lo(test_true)
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(test_true)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:  .LBB0_2: # %true
-; RV32I-NEXT:    jalr a0
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB0_3: # %false
-; RV32I-NEXT:    lui a0, %hi(test_false)
-; RV32I-NEXT:    addi a0, a0, %lo(test_false)
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(test_false)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    j .LBB0_2
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !0
 
 ; Expected layout order is: Entry, TrueBlock, FalseBlock
 ; Entry->TrueBlock is the common path, which should be taken whenever the
 ; conditional branch is false.
 

 define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
 ; RV32I-LABEL: test_bcc_fallthrough_nottaken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a1, zero, 42
 ; RV32I-NEXT:    beq a0, a1, .LBB1_3
 ; RV32I-NEXT:  # %bb.1: # %false
-; RV32I-NEXT:    lui a0, %hi(test_false)
-; RV32I-NEXT:    addi a0, a0, %lo(test_false)
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(test_false)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:  .LBB1_2: # %true
-; RV32I-NEXT:    jalr a0
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_3: # %true
-; RV32I-NEXT:    lui a0, %hi(test_true)
-; RV32I-NEXT:    addi a0, a0, %lo(test_true)
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(test_true)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    j .LBB1_2
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !1
 
 ; Expected layout order is: Entry, FalseBlock, TrueBlock
 ; Entry->FalseBlock is the common path, which should be taken whenever the
 ; conditional branch is false
 

test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB3_3
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    addi a0, zero, 8
 ; RV32I-NEXT:  .LBB3_3: # %cond.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB4_3
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    addi a0, zero, 16
 ; RV32I-NEXT:  .LBB4_3: # %cond.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB5_3
 ; RV32I-NEXT:  .LBB5_2:
 ; RV32I-NEXT:    addi a0, zero, 32
 ; RV32I-NEXT:  .LBB5_3: # %cond.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB6_3
 ; RV32I-NEXT:  .LBB6_2:
 ; RV32I-NEXT:    addi a0, zero, 32
 ; RV32I-NEXT:  .LBB6_3: # %cond.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
   ret i32 %tmp
 }
 
 define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I-LABEL: test_cttz_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
-; RV32I-NEXT:    sw s7, 16(sp)
-; RV32I-NEXT:    sw s8, 12(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s6, 4(sp)
+; RV32I-NEXT:    sw s7, 0(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525
 ; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi s6, a1, 819
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi s4, a1, 257
-; RV32I-NEXT:    lui a1, %hi(__mulsi3)
-; RV32I-NEXT:    addi s7, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s8, a1, -241
-; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    addi s7, a1, -241
+; RV32I-NEXT:    and a0, a0, s7
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    jalr s7
+; RV32I-NEXT:  .Ltmp4:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    addi a0, s2, -1
 ; RV32I-NEXT:    not a1, s2
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    and a0, a0, s7
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    jalr s7
+; RV32I-NEXT:  .Ltmp5:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-NEXT:    bnez s3, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:    j .LBB7_3
 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    srli a0, s1, 24
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    mv a1, zero
-; RV32I-NEXT:    lw s8, 12(sp)
-; RV32I-NEXT:    lw s7, 16(sp)
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s7, 0(sp)
+; RV32I-NEXT:    lw s6, 4(sp)
+; RV32I-NEXT:    lw s5, 8(sp)
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
   %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
   ret i64 %tmp
 }
 
 define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
 ; RV32I-LABEL: test_cttz_i8_zero_undef:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp6:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
   ret i8 %tmp
 }
 

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp7:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
   ret i16 %tmp
 }
 

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp8:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp8)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %tmp = call i32 @llvm.cttz.i32(i32 %a, i1 true)
   ret i32 %tmp
 }
 
 define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I-LABEL: test_cttz_i64_zero_undef:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    sw s1, 40(sp)
-; RV32I-NEXT:    sw s2, 36(sp)
-; RV32I-NEXT:    sw s3, 32(sp)
-; RV32I-NEXT:    sw s4, 28(sp)
-; RV32I-NEXT:    sw s5, 24(sp)
-; RV32I-NEXT:    sw s6, 20(sp)
-; RV32I-NEXT:    sw s7, 16(sp)
-; RV32I-NEXT:    sw s8, 12(sp)
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s1, 24(sp)
+; RV32I-NEXT:    sw s2, 20(sp)
+; RV32I-NEXT:    sw s3, 16(sp)
+; RV32I-NEXT:    sw s4, 12(sp)
+; RV32I-NEXT:    sw s5, 8(sp)
+; RV32I-NEXT:    sw s6, 4(sp)
+; RV32I-NEXT:    sw s7, 0(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525
 ; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi s6, a1, 819
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi s4, a1, 257
-; RV32I-NEXT:    lui a1, %hi(__mulsi3)
-; RV32I-NEXT:    addi s7, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s8, a1, -241
-; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    addi s7, a1, -241
+; RV32I-NEXT:    and a0, a0, s7
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    jalr s7
+; RV32I-NEXT:  .Ltmp9:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp9)
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    addi a0, s2, -1
 ; RV32I-NEXT:    not a1, s2
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    and a0, a0, s7
 ; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    jalr s7
+; RV32I-NEXT:  .Ltmp10:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp10)
 ; RV32I-NEXT:    bnez s3, .LBB11_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:    j .LBB11_3
 ; RV32I-NEXT:  .LBB11_2:
 ; RV32I-NEXT:    srli a0, s1, 24
 ; RV32I-NEXT:  .LBB11_3:
 ; RV32I-NEXT:    mv a1, zero
-; RV32I-NEXT:    lw s8, 12(sp)
-; RV32I-NEXT:    lw s7, 16(sp)
-; RV32I-NEXT:    lw s6, 20(sp)
-; RV32I-NEXT:    lw s5, 24(sp)
-; RV32I-NEXT:    lw s4, 28(sp)
-; RV32I-NEXT:    lw s3, 32(sp)
-; RV32I-NEXT:    lw s2, 36(sp)
-; RV32I-NEXT:    lw s1, 40(sp)
-; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    addi sp, sp, 48
+; RV32I-NEXT:    lw s7, 0(sp)
+; RV32I-NEXT:    lw s6, 4(sp)
+; RV32I-NEXT:    lw s5, 8(sp)
+; RV32I-NEXT:    lw s4, 12(sp)
+; RV32I-NEXT:    lw s3, 16(sp)
+; RV32I-NEXT:    lw s2, 20(sp)
+; RV32I-NEXT:    lw s1, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
   %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true)
   ret i64 %tmp
 }
 
 define i32 @test_ctpop_i32(i32 %a) nounwind {
 ; RV32I-LABEL: test_ctpop_i32:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp11:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp11)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call i32 @llvm.ctpop.i32(i32 %a)
   ret i32 %1
 }

test/CodeGen/RISCV/byval.ll

 ; RV32I-NEXT:    lw a0, %lo(foo+8)(a0)
 ; RV32I-NEXT:    sw a0, 20(sp)
 ; RV32I-NEXT:    lui a0, %hi(foo+4)
 ; RV32I-NEXT:    lw a0, %lo(foo+4)(a0)
 ; RV32I-NEXT:    sw a0, 16(sp)
 ; RV32I-NEXT:    lui a0, %hi(foo)
 ; RV32I-NEXT:    lw a0, %lo(foo)(a0)
 ; RV32I-NEXT:    sw a0, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(callee)
-; RV32I-NEXT:    addi a1, a0, %lo(callee)
 ; RV32I-NEXT:    addi a0, sp, 12
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(callee)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 entry:
   %call = call i32 @callee(%struct.Foo* byval @foo)
   ret void
 }

test/CodeGen/RISCV/calling-conv-sext-zext.ll

 
 declare void @receive_uint8(i8 zeroext)
 
 define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind {
 ; RV32I-LABEL: pass_uint8_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   call void @receive_uint8(i8 zeroext %a)
   ret void
 }
 
 declare zeroext i8 @return_uint8()
 
 define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
 ; RV32I-LABEL: ret_callresult_uint8_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call zeroext i8 @return_uint8()
   ret i8 %1
 }
 
 define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind {
 ; RV32I-LABEL: uint8_arg_to_sint8_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    ret
   ret i8 %a
 }
 
 declare void @receive_sint8(i8 signext)
 
 define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind {
 ; RV32I-LABEL: pass_uint8_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 
   call void @receive_sint8(i8 signext %a)
   ret void
 }
 
 define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
 ; RV32I-LABEL: ret_callresult_uint8_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call zeroext i8 @return_uint8()
   ret i8 %1
 }
 
 define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind {
 ; RV32I-LABEL: uint8_arg_to_anyint32_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
   %1 = zext i8 %a to i32
   ret i32 %1
 }
 
 declare void @receive_anyint32(i32 signext)
 
 define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind {
 ; RV32I-LABEL: pass_uint8_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp4:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = zext i8 %a to i32
   call void @receive_anyint32(i32 signext %1)
   ret void
 }
 
 define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
 ; RV32I-LABEL: ret_callresult_uint8_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_uint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp5:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call zeroext i8 @return_uint8()
   %2 = zext i8 %1 to i32
   ret i32 %2
 }
 
 define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind {
 ; RV32I-LABEL: sint8_arg_to_uint8_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    ret
   ret i8 %a
 }
 
 define void @pass_sint8_as_uint8(i8 signext %a) nounwind {
 ; RV32I-LABEL: pass_sint8_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp6:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   call void @receive_uint8(i8 zeroext %a)
   ret void
 }
 
 declare signext i8 @return_sint8()
 
 define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
 ; RV32I-LABEL: ret_callresult_sint8_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp7:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i8 @return_sint8()
   ret i8 %1
 }
 
 define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind {
 ; RV32I-LABEL: sint8_arg_to_sint8_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
   ret i8 %a
 }
 
 define void @pass_sint8_as_sint8(i8 signext %a) nounwind {
 ; RV32I-LABEL: pass_sint8_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp8:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp8)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   call void @receive_sint8(i8 signext %a)
   ret void
 }
 
 define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
 ; RV32I-LABEL: ret_callresult_sint8_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp9:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp9)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i8 @return_sint8()
   ret i8 %1
 }
 
 define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind {
 ; RV32I-LABEL: sint8_arg_to_anyint32_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
   %1 = sext i8 %a to i32
   ret i32 %1
 }
 
 define void @pass_sint8_as_anyint32(i8 signext %a) nounwind {
 ; RV32I-LABEL: pass_sint8_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp10:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp10)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = sext i8 %a to i32
   call void @receive_anyint32(i32 signext %1)
   ret void
 }
 
 define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
 ; RV32I-LABEL: ret_callresult_sint8_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_sint8)
-; RV32I-NEXT:    addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp11:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp11)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i8 @return_sint8()
   %2 = sext i8 %1 to i32
   ret i32 %2
 }
 
 define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind {
 ; RV32I-LABEL: anyint32_arg_to_uint8_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    ret
   %1 = trunc i32 %a to i8
   ret i8 %1
 }
 
 define void @pass_anyint32_as_uint8(i32 signext %a) nounwind {
 ; RV32I-LABEL: pass_anyint32_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    lui a1, %hi(receive_uint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp12:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_uint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp12)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = trunc i32 %a to i8
   call void @receive_uint8(i8 zeroext %1)
   ret void
 }
 
 declare signext i32 @return_anyint32()
 
 define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
 ; RV32I-LABEL: ret_callresult_anyint32_as_uint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp13:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp13)
 ; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i32 @return_anyint32()
   %2 = trunc i32 %1 to i8
   ret i8 %2
 }
 
 define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind {
 ; RV32I-LABEL: anyint32_arg_to_sint8_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    ret
   %1 = trunc i32 %a to i8
   ret i8 %1
 }
 
 define void @pass_anyint32_as_sint8(i32 signext %a) nounwind {
 ; RV32I-LABEL: pass_anyint32_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_sint8)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_sint8)
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp14:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_sint8)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp14)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = trunc i32 %a to i8
   call void @receive_sint8(i8 signext %1)
   ret void
 }
 
 define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
 ; RV32I-LABEL: ret_callresult_anyint32_as_sint8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp15:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp15)
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i32 @return_anyint32()
   %2 = trunc i32 %1 to i8
   ret i8 %2
 }
 
 define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind {
 ; RV32I-LABEL: anyint32_arg_to_anyint32_ret:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
   ret i32 %a
 }
 
 define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind {
 ; RV32I-LABEL: pass_anyint32_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(receive_anyint32)
-; RV32I-NEXT:    addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp16:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(receive_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp16)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   call void @receive_anyint32(i32 signext %a)
   ret void
 }
 
 define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
 ; RV32I-LABEL: ret_callresult_anyint32_as_anyint32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a0, %hi(return_anyint32)
-; RV32I-NEXT:    addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT:    jalr a0
+; RV32I-NEXT:  .Ltmp17:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(return_anyint32)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp17)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call signext i32 @return_anyint32()
   ret i32 %1
 }
 

test/CodeGen/RISCV/calling-conv.ll

 ; RV32I-FPELIM-NEXT:    sw s1, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw s2, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw s3, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw s4, 12(sp)
 ; RV32I-FPELIM-NEXT:    mv s1, a4
 ; RV32I-FPELIM-NEXT:    mv s2, a3
 ; RV32I-FPELIM-NEXT:    mv s3, a1
 ; RV32I-FPELIM-NEXT:    mv s4, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(__fixdfsi)
-; RV32I-FPELIM-NEXT:    addi a2, a0, %lo(__fixdfsi)
 ; RV32I-FPELIM-NEXT:    mv a0, a5
 ; RV32I-FPELIM-NEXT:    mv a1, a6
-; RV32I-FPELIM-NEXT:    jalr a2
+; RV32I-FPELIM-NEXT:  .Ltmp0:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(__fixdfsi)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-FPELIM-NEXT:    add a1, s4, s3
 ; RV32I-FPELIM-NEXT:    add a1, a1, s2
 ; RV32I-FPELIM-NEXT:    add a1, a1, s1
 ; RV32I-FPELIM-NEXT:    add a0, a1, a0
 ; RV32I-FPELIM-NEXT:    lw s4, 12(sp)
 ; RV32I-FPELIM-NEXT:    lw s3, 16(sp)
 ; RV32I-FPELIM-NEXT:    lw s2, 20(sp)
 ; RV32I-FPELIM-NEXT:    lw s1, 24(sp)

 ; RV32I-WITHFP-NEXT:    sw s2, 16(sp)
 ; RV32I-WITHFP-NEXT:    sw s3, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s4, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
 ; RV32I-WITHFP-NEXT:    mv s1, a4
 ; RV32I-WITHFP-NEXT:    mv s2, a3
 ; RV32I-WITHFP-NEXT:    mv s3, a1
 ; RV32I-WITHFP-NEXT:    mv s4, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(__fixdfsi)
-; RV32I-WITHFP-NEXT:    addi a2, a0, %lo(__fixdfsi)
 ; RV32I-WITHFP-NEXT:    mv a0, a5
 ; RV32I-WITHFP-NEXT:    mv a1, a6
-; RV32I-WITHFP-NEXT:    jalr a2
+; RV32I-WITHFP-NEXT:  .Ltmp0:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(__fixdfsi)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-WITHFP-NEXT:    add a1, s4, s3
 ; RV32I-WITHFP-NEXT:    add a1, a1, s2
 ; RV32I-WITHFP-NEXT:    add a1, a1, s1
 ; RV32I-WITHFP-NEXT:    add a0, a1, a0
 ; RV32I-WITHFP-NEXT:    lw s4, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw s3, 12(sp)
 ; RV32I-WITHFP-NEXT:    lw s2, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw s1, 20(sp)

 
 define i32 @caller_scalars() nounwind {
 ; RV32I-FPELIM-LABEL: caller_scalars:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 262464
 ; RV32I-FPELIM-NEXT:    mv a6, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_scalars)
-; RV32I-FPELIM-NEXT:    addi a7, a0, %lo(callee_scalars)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 4
 ; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    mv a5, zero
-; RV32I-FPELIM-NEXT:    jalr a7
+; RV32I-FPELIM-NEXT:  .Ltmp1:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_scalars)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a0, 262464
 ; RV32I-WITHFP-NEXT:    mv a6, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_scalars)
-; RV32I-WITHFP-NEXT:    addi a7, a0, %lo(callee_scalars)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 4
 ; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    mv a5, zero
-; RV32I-WITHFP-NEXT:    jalr a7
+; RV32I-WITHFP-NEXT:  .Ltmp1:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_scalars)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_scalars(i32 1, i64 2, i32 3, i32 4, double 5.000000e+00)
   ret i32 %1
 }
 

 ; RV32I-FPELIM-NEXT:    sw zero, 36(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 32(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    sw a0, 24(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 524272
 ; RV32I-FPELIM-NEXT:    mv a0, a0
 ; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_scalars)
-; RV32I-FPELIM-NEXT:    addi a2, a0, %lo(callee_large_scalars)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 24
 ; RV32I-FPELIM-NEXT:    mv a1, sp
-; RV32I-FPELIM-NEXT:    jalr a2
+; RV32I-FPELIM-NEXT:  .Ltmp2:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_large_scalars)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-FPELIM-NEXT:    lw ra, 44(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -48
 ; RV32I-WITHFP-NEXT:    sw ra, 44(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 40(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 48
 ; RV32I-WITHFP-NEXT:    sw zero, -40(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -44(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -48(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -12(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 524272
 ; RV32I-WITHFP-NEXT:    mv a0, a0
 ; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_scalars)
-; RV32I-WITHFP-NEXT:    addi a2, a0, %lo(callee_large_scalars)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -24
 ; RV32I-WITHFP-NEXT:    addi a1, s0, -48
-; RV32I-WITHFP-NEXT:    jalr a2
+; RV32I-WITHFP-NEXT:  .Ltmp2:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_large_scalars)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-WITHFP-NEXT:    lw s0, 40(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 44(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
   ret i32 %1
 }
 

 ; RV32I-FPELIM-NEXT:    sw zero, 52(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 48(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 44(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 8
 ; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 524272
 ; RV32I-FPELIM-NEXT:    mv a0, a0
 ; RV32I-FPELIM-NEXT:    sw a0, 28(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_scalars_exhausted_regs)
-; RV32I-FPELIM-NEXT:    addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a2, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 5
 ; RV32I-FPELIM-NEXT:    addi a5, zero, 6
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 7
 ; RV32I-FPELIM-NEXT:    addi a7, sp, 40
-; RV32I-FPELIM-NEXT:    jalr t0
+; RV32I-FPELIM-NEXT:  .Ltmp3:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_large_scalars_exhausted_regs)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 64
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -64
 ; RV32I-WITHFP-NEXT:    sw ra, 60(sp)

 ; RV32I-WITHFP-NEXT:    sw zero, -12(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 524272
 ; RV32I-WITHFP-NEXT:    mv a0, a0
 ; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_scalars_exhausted_regs)
-; RV32I-WITHFP-NEXT:    addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a2, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 5
 ; RV32I-WITHFP-NEXT:    addi a5, zero, 6
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 7
 ; RV32I-WITHFP-NEXT:    addi a7, s0, -24
-; RV32I-WITHFP-NEXT:    jalr t0
+; RV32I-WITHFP-NEXT:  .Ltmp3:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_large_scalars_exhausted_regs)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 64
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_large_scalars_exhausted_regs(
       i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
       fp128 0xL00000000000000007FFF000000000000)
   ret i32 %1
 }
 
 ; Ensure that libcalls generated in the middle-end obey the calling convention
 
 define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
 ; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    mv a2, a1
 ; RV32I-FPELIM-NEXT:    mv a1, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(__floatditf)
-; RV32I-FPELIM-NEXT:    addi a3, a0, %lo(__floatditf)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 8
-; RV32I-FPELIM-NEXT:    jalr a3
+; RV32I-FPELIM-NEXT:  .Ltmp4:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(__floatditf)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-FPELIM-NEXT:    lw a0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -32
 ; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
 ; RV32I-WITHFP-NEXT:    mv a2, a1
 ; RV32I-WITHFP-NEXT:    mv a1, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(__floatditf)
-; RV32I-WITHFP-NEXT:    addi a3, a0, %lo(__floatditf)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -24
-; RV32I-WITHFP-NEXT:    jalr a3
+; RV32I-WITHFP-NEXT:  .Ltmp4:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(__floatditf)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-WITHFP-NEXT:    lw a0, -24(s0)
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %1 = sitofp i64 %a to fp128
   %2 = bitcast fp128 %1 to i128
   %3 = trunc i128 %2 to i32

 define i32 @caller_many_scalars() nounwind {
 ; RV32I-FPELIM-LABEL: caller_many_scalars:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 8
 ; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 0(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_many_scalars)
-; RV32I-FPELIM-NEXT:    addi t0, a0, %lo(callee_many_scalars)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a2, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a5, zero, 5
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 6
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 7
 ; RV32I-FPELIM-NEXT:    mv a4, zero
-; RV32I-FPELIM-NEXT:    jalr t0
+; RV32I-FPELIM-NEXT:  .Ltmp5:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_many_scalars)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_many_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 8
 ; RV32I-WITHFP-NEXT:    sw a0, 4(sp)
 ; RV32I-WITHFP-NEXT:    sw zero, 0(sp)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_many_scalars)
-; RV32I-WITHFP-NEXT:    addi t0, a0, %lo(callee_many_scalars)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a2, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a5, zero, 5
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 6
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 7
 ; RV32I-WITHFP-NEXT:    mv a4, zero
-; RV32I-WITHFP-NEXT:    jalr t0
+; RV32I-WITHFP-NEXT:  .Ltmp5:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_many_scalars)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
   ret i32 %1
 }
 
; RV32I-WITHFP-NEXT:    ret
   ret i32 %4
 }
 
 define i32 @caller_small_coerced_struct() nounwind {
 ; RV32I-FPELIM-LABEL: caller_small_coerced_struct:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_small_coerced_struct)
-; RV32I-FPELIM-NEXT:    addi a2, a0, %lo(callee_small_coerced_struct)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
-; RV32I-FPELIM-NEXT:    jalr a2
+; RV32I-FPELIM-NEXT:  .Ltmp6:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_small_coerced_struct)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_small_coerced_struct:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_small_coerced_struct)
-; RV32I-WITHFP-NEXT:    addi a2, a0, %lo(callee_small_coerced_struct)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
-; RV32I-WITHFP-NEXT:    jalr a2
+; RV32I-WITHFP-NEXT:  .Ltmp6:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_small_coerced_struct)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2])
   ret i32 %1
 }
 

 ; RV32I-FPELIM-NEXT:    sw a0, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 3
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
 ; RV32I-FPELIM-NEXT:    sw a0, 16(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 4
 ; RV32I-FPELIM-NEXT:    sw a0, 36(sp)
 ; RV32I-FPELIM-NEXT:    sw a0, 20(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_struct)
-; RV32I-FPELIM-NEXT:    addi a1, a0, %lo(callee_large_struct)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 8
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp7:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_large_struct)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-FPELIM-NEXT:    lw ra, 44(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_struct:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -48
 ; RV32I-WITHFP-NEXT:    sw ra, 44(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 40(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 48
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
 ; RV32I-WITHFP-NEXT:    sw a0, -40(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 2
 ; RV32I-WITHFP-NEXT:    sw a0, -20(s0)
 ; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 3
 ; RV32I-WITHFP-NEXT:    sw a0, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 4
 ; RV32I-WITHFP-NEXT:    sw a0, -12(s0)
 ; RV32I-WITHFP-NEXT:    sw a0, -28(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_struct)
-; RV32I-WITHFP-NEXT:    addi a1, a0, %lo(callee_large_struct)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -40
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp7:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_large_struct)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-WITHFP-NEXT:    lw s0, 40(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 44(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %ls = alloca %struct.large, align 4
   %1 = bitcast %struct.large* %ls to i8*
   %a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0
   store i32 1, i32* %a

 ; RV32I-FPELIM-NEXT:    lui a0, 964690
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -328
 ; RV32I-FPELIM-NEXT:    sw a0, 36(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a5, a0, -2048
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_aligned_stack)
-; RV32I-FPELIM-NEXT:    addi t0, a0, %lo(callee_aligned_stack)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 14
-; RV32I-FPELIM-NEXT:    jalr t0
+; RV32I-FPELIM-NEXT:  .Ltmp8:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_aligned_stack)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp8)
 ; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 64
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_aligned_stack:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -64
 ; RV32I-WITHFP-NEXT:    sw ra, 60(sp)

 ; RV32I-WITHFP-NEXT:    lui a0, 964690
 ; RV32I-WITHFP-NEXT:    addi a0, a0, -328
 ; RV32I-WITHFP-NEXT:    sw a0, -28(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 335544
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 1311
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 688509
 ; RV32I-WITHFP-NEXT:    addi a5, a0, -2048
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_aligned_stack)
-; RV32I-WITHFP-NEXT:    addi t0, a0, %lo(callee_aligned_stack)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 14
-; RV32I-WITHFP-NEXT:    jalr t0
+; RV32I-WITHFP-NEXT:  .Ltmp8:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_aligned_stack)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp8)
 ; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 64
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
     i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
     [2 x i32] [i32 17, i32 18])
; RV32I-WITHFP-NEXT:    ret
   ret i64 1234567898765
 }
 
 define i32 @caller_small_scalar_ret() nounwind {
 ; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_small_scalar_ret)
-; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(callee_small_scalar_ret)
-; RV32I-FPELIM-NEXT:    jalr a0
-; RV32I-FPELIM-NEXT:    lui a2, 56
-; RV32I-FPELIM-NEXT:    addi a2, a2, 580
-; RV32I-FPELIM-NEXT:    xor a1, a1, a2
+; RV32I-FPELIM-NEXT:    sw s1, 8(sp)
+; RV32I-FPELIM-NEXT:    lui a0, 56
+; RV32I-FPELIM-NEXT:    addi s1, a0, 580
+; RV32I-FPELIM-NEXT:  .Ltmp9:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_small_scalar_ret)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp9)
+; RV32I-FPELIM-NEXT:    xor a1, a1, s1
 ; RV32I-FPELIM-NEXT:    lui a2, 200614
 ; RV32I-FPELIM-NEXT:    addi a2, a2, 647
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a2
 ; RV32I-FPELIM-NEXT:    or a0, a0, a1
 ; RV32I-FPELIM-NEXT:    xor a0, a0, zero
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
+; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
+; RV32I-WITHFP-NEXT:    sw s1, 4(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_small_scalar_ret)
-; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(callee_small_scalar_ret)
-; RV32I-WITHFP-NEXT:    jalr a0
-; RV32I-WITHFP-NEXT:    lui a2, 56
-; RV32I-WITHFP-NEXT:    addi a2, a2, 580
-; RV32I-WITHFP-NEXT:    xor a1, a1, a2
+; RV32I-WITHFP-NEXT:    lui a0, 56
+; RV32I-WITHFP-NEXT:    addi s1, a0, 580
+; RV32I-WITHFP-NEXT:  .Ltmp9:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_small_scalar_ret)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp9)
+; RV32I-WITHFP-NEXT:    xor a1, a1, s1
 ; RV32I-WITHFP-NEXT:    lui a2, 200614
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 647
 ; RV32I-WITHFP-NEXT:    xor a0, a0, a2
 ; RV32I-WITHFP-NEXT:    or a0, a0, a1
 ; RV32I-WITHFP-NEXT:    xor a0, a0, zero
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
+; RV32I-WITHFP-NEXT:    lw s1, 4(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i64 @callee_small_scalar_ret()
   %2 = icmp eq i64 987654321234567, %1
   %3 = zext i1 %2 to i32
   ret i32 %3
; RV32I-WITHFP-NEXT:    ret
   ret %struct.small { i32 1, i32* null }
 }
 
 define i32 @caller_small_struct_ret() nounwind {
 ; RV32I-FPELIM-LABEL: caller_small_struct_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_small_struct_ret)
-; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(callee_small_struct_ret)
-; RV32I-FPELIM-NEXT:    jalr a0
+; RV32I-FPELIM-NEXT:  .Ltmp10:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_small_struct_ret)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp10)
 ; RV32I-FPELIM-NEXT:    add a0, a0, a1
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_small_struct_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_small_struct_ret)
-; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(callee_small_struct_ret)
-; RV32I-WITHFP-NEXT:    jalr a0
+; RV32I-WITHFP-NEXT:  .Ltmp10:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_small_struct_ret)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp10)
 ; RV32I-WITHFP-NEXT:    add a0, a0, a1
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call %struct.small @callee_small_struct_ret()
   %2 = extractvalue %struct.small %1, 0
   %3 = extractvalue %struct.small %1, 1
; RV32I-WITHFP-NEXT:    ret
   ret fp128 0xL00000000000000007FFF000000000000
 }
 
 define void @caller_large_scalar_ret() nounwind {
 ; RV32I-FPELIM-LABEL: caller_large_scalar_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_scalar_ret)
-; RV32I-FPELIM-NEXT:    addi a1, a0, %lo(callee_large_scalar_ret)
 ; RV32I-FPELIM-NEXT:    mv a0, sp
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp11:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_large_scalar_ret)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp11)
 ; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_scalar_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -32
 ; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_scalar_ret)
-; RV32I-WITHFP-NEXT:    addi a1, a0, %lo(callee_large_scalar_ret)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -32
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp11:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_large_scalar_ret)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp11)
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call fp128 @callee_large_scalar_ret()
   ret void
 }
 
; RV32I-WITHFP-NEXT:    ret
   ret void
 }
 
 define i32 @caller_large_struct_ret() nounwind {
 ; RV32I-FPELIM-LABEL: caller_large_struct_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_struct_ret)
-; RV32I-FPELIM-NEXT:    addi a1, a0, %lo(callee_large_struct_ret)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 8
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp12:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(callee_large_struct_ret)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp12)
 ; RV32I-FPELIM-NEXT:    lw a0, 20(sp)
 ; RV32I-FPELIM-NEXT:    lw a1, 8(sp)
 ; RV32I-FPELIM-NEXT:    add a0, a1, a0
 ; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_struct_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -32
 ; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
-; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_struct_ret)
-; RV32I-WITHFP-NEXT:    addi a1, a0, %lo(callee_large_struct_ret)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -24
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp12:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(callee_large_struct_ret)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp12)
 ; RV32I-WITHFP-NEXT:    lw a0, -12(s0)
 ; RV32I-WITHFP-NEXT:    lw a1, -24(s0)
 ; RV32I-WITHFP-NEXT:    add a0, a1, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %1 = alloca %struct.large
   call void @callee_large_struct_ret(%struct.large* sret %1)
   %2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
   %3 = load i32, i32* %2
   %4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3
   %5 = load i32, i32* %4
   %6 = add i32 %3, %5
   ret i32 %6
 }

test/CodeGen/RISCV/calls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 
 declare i32 @external_function(i32)
 
 define i32 @test_call_external(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_external:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(external_function)
-; RV32I-NEXT:    addi a1, a1, %lo(external_function)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(external_function)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call i32 @external_function(i32 %a)
   ret i32 %1
 }
 
 define i32 @defined_function(i32 %a) nounwind {
 ; RV32I-LABEL: defined_function:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    ret
   %1 = add i32 %a, 1
   ret i32 %1
 }
 
 define i32 @test_call_defined(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_defined:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(defined_function)
-; RV32I-NEXT:    addi a1, a1, %lo(defined_function)
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(defined_function)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call i32 @defined_function(i32 %a)
   ret i32 %1
 }
 
 define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {

 
 define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: test_call_fastcc:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s1, 8(sp)
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, %hi(fastcc_function)
-; RV32I-NEXT:    addi a2, a0, %lo(fastcc_function)
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(fastcc_function)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    lw s1, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
   ret i32 %a
 }
 
 declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
 
 define i32 @test_call_external_many_args(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_external_many_args:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s1, 8(sp)
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    sw a0, 4(sp)
 ; RV32I-NEXT:    sw a0, 0(sp)
-; RV32I-NEXT:    lui a0, %hi(external_many_args)
-; RV32I-NEXT:    addi t0, a0, %lo(external_many_args)
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s1
-; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    mv a4, s1
-; RV32I-NEXT:    mv a5, s1
-; RV32I-NEXT:    mv a6, s1
-; RV32I-NEXT:    mv a7, s1
-; RV32I-NEXT:    jalr t0
+; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    mv a2, a0
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    mv a4, a0
+; RV32I-NEXT:    mv a5, a0
+; RV32I-NEXT:    mv a6, a0
+; RV32I-NEXT:    mv a7, a0
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(external_many_args)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    lw s1, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
                                     i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
   ret i32 %a

 
 define i32 @test_call_defined_many_args(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_defined_many_args:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw a0, 4(sp)
 ; RV32I-NEXT:    sw a0, 0(sp)
-; RV32I-NEXT:    lui a1, %hi(defined_many_args)
-; RV32I-NEXT:    addi t0, a1, %lo(defined_many_args)
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    mv a5, a0
 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    mv a7, a0
-; RV32I-NEXT:    jalr t0
+; RV32I-NEXT:  .Ltmp4:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(defined_many_args)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
                                    i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
   ret i32 %1
 }

test/CodeGen/RISCV/compress-Pseudo.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+c  -riscv-no-aliases -o %t1 < %s
 ; RUN: FileCheck %s < %t1
 
 define void @foo() {
 ; CHECK-LABEL: foo:
 ; CHECK:   c.jr
-
 end:
   ret void
 }

test/CodeGen/RISCV/compress-inline-asm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+c  -filetype=obj < %s\
 ; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -riscv-no-aliases -\
 ; RUN: | FileCheck -check-prefix=CHECK %s
 
 @ext = external global i32
 
 define i32 @compress_test(i32 %a) {
 ; CHECK-LABEL: compress_test:
 ; CHECK:    c.add a0, a1
 ; CHECK-NEXT:    c.jr ra
   %1 = load i32, i32* @ext
   %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
   ret i32 %2
 }
 

test/CodeGen/RISCV/div.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @udiv(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: udiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__udivsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__udivsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__udivsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: udiv:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    divu a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
 }
 
 define i32 @udiv_constant(i32 %a) nounwind {
 ; RV32I-LABEL: udiv_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(__udivsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__udivsi3)
 ; RV32I-NEXT:    addi a1, zero, 5
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__udivsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: udiv_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    lui a1, 838861
 ; RV32IM-NEXT:    addi a1, a1, -819
; RV32IM-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @udiv64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: udiv64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a4, %hi(__udivdi3)
-; RV32I-NEXT:    addi a4, a4, %lo(__udivdi3)
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__udivdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: udiv64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    lui a4, %hi(__udivdi3)
-; RV32IM-NEXT:    addi a4, a4, %lo(__udivdi3)
-; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:  .Ltmp0:
+; RV32IM-NEXT:    auipc ra, %pcrel_hi(__udivdi3)
+; RV32IM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32IM-NEXT:    lw ra, 12(sp)
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
   %1 = udiv i64 %a, %b
   ret i64 %1
 }
 
 define i64 @udiv64_constant(i64 %a) nounwind {
 ; RV32I-LABEL: udiv64_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__udivdi3)
-; RV32I-NEXT:    addi a4, a2, %lo(__udivdi3)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__udivdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: udiv64_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    lui a2, %hi(__udivdi3)
-; RV32IM-NEXT:    addi a4, a2, %lo(__udivdi3)
 ; RV32IM-NEXT:    addi a2, zero, 5
 ; RV32IM-NEXT:    mv a3, zero
-; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:  .Ltmp1:
+; RV32IM-NEXT:    auipc ra, %pcrel_hi(__udivdi3)
+; RV32IM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32IM-NEXT:    lw ra, 12(sp)
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
   %1 = udiv i64 %a, 5
   ret i64 %1
 }
 
 define i32 @sdiv(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sdiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__divsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__divsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp4:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__divsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    div a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
 }
 
 define i32 @sdiv_constant(i32 %a) nounwind {
 ; RV32I-LABEL: sdiv_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(__divsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__divsi3)
 ; RV32I-NEXT:    addi a1, zero, 5
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp5:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__divsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    lui a1, 419430
 ; RV32IM-NEXT:    addi a1, a1, 1639
; RV32IM-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @sdiv64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: sdiv64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a4, %hi(__divdi3)
-; RV32I-NEXT:    addi a4, a4, %lo(__divdi3)
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp6:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__divdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    lui a4, %hi(__divdi3)
-; RV32IM-NEXT:    addi a4, a4, %lo(__divdi3)
-; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:  .Ltmp2:
+; RV32IM-NEXT:    auipc ra, %pcrel_hi(__divdi3)
+; RV32IM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32IM-NEXT:    lw ra, 12(sp)
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
   %1 = sdiv i64 %a, %b
   ret i64 %1
 }
 
 define i64 @sdiv64_constant(i64 %a) nounwind {
 ; RV32I-LABEL: sdiv64_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__divdi3)
-; RV32I-NEXT:    addi a4, a2, %lo(__divdi3)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp7:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__divdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv64_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    lui a2, %hi(__divdi3)
-; RV32IM-NEXT:    addi a4, a2, %lo(__divdi3)
 ; RV32IM-NEXT:    addi a2, zero, 5
 ; RV32IM-NEXT:    mv a3, zero
-; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:  .Ltmp3:
+; RV32IM-NEXT:    auipc ra, %pcrel_hi(__divdi3)
+; RV32IM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32IM-NEXT:    lw ra, 12(sp)
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
   %1 = sdiv i64 %a, 5
   ret i64 %1
 }

test/CodeGen/RISCV/float-br-fcmp.ll

 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    addi a0, zero, 1
 ; RV32IF-NEXT:    bnez a0, .LBB0_2
 ; RV32IF-NEXT:  # %bb.1: # %if.then
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB0_2: # %if.else
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp0:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
   %1 = fcmp false float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   ret void
 if.else:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_oeq(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_oeq:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    feq.s a0, ft1, ft0
 ; RV32IF-NEXT:    bnez a0, .LBB1_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB1_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp1:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
   %1 = fcmp oeq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV32IF-NEXT:    feq.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    beqz a0, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB2_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp2:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
   %1 = fcmp oeq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   tail call void @abort()
   unreachable
 if.else:
   ret void
 }
 
 define void @br_fcmp_ogt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ogt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    bnez a0, .LBB3_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB3_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp3:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
   %1 = fcmp ogt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_oge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_oge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    bnez a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB4_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp4:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
   %1 = fcmp oge float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_olt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_olt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    bnez a0, .LBB5_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB5_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp5:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
   %1 = fcmp olt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ole(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ole:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    bnez a0, .LBB6_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB6_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp6:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
   %1 = fcmp ole float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    and a0, a1, a0
 ; RV32IF-NEXT:    bnez a0, .LBB7_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB7_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp7:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
   %1 = fcmp one float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB8_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB8_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp8:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp8)
   %1 = fcmp ord float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV32IF-NEXT:    seqz a1, a1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    bnez a0, .LBB9_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB9_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp9:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp9)
   %1 = fcmp ueq float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ugt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ugt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB10_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB10_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp10:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp10)
   %1 = fcmp ugt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_uge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB11_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB11_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp11:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp11)
   %1 = fcmp uge float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ult(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ult:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB12_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp12:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp12)
   %1 = fcmp ult float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ule(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ule:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB13_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB13_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp13:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp13)
   %1 = fcmp ule float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_une(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_une:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    feq.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB14_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB14_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp14:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp14)
   %1 = fcmp une float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    bnez a0, .LBB15_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB15_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp15:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp15)
   %1 = fcmp uno float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_true(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_true:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    addi a0, zero, 1
 ; RV32IF-NEXT:    bnez a0, .LBB16_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB16_2: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp16:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp16)
   %1 = fcmp true float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 ; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
 ; and RISCVInstrInfo::loadRegFromStackSlot
 define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
 ; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
 ; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
-; RV32IF-NEXT:    sw s1, 8(sp)
-; RV32IF-NEXT:    lui a0, %hi(dummy)
-; RV32IF-NEXT:    addi s1, a0, %lo(dummy)
 ; RV32IF-NEXT:    mv a0, zero
-; RV32IF-NEXT:    jalr s1
+; RV32IF-NEXT:  .Ltmp17:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(dummy)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp17)
+; RV32IF-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV32IF-NEXT:    addi a1, a1, %lo(.LCPI17_0)
+; RV32IF-NEXT:    flw ft1, 0(a1)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
-; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI17_0)
-; RV32IF-NEXT:    flw ft1, 0(a0)
-; RV32IF-NEXT:    fsw ft1, 4(sp)
+; RV32IF-NEXT:    fsw ft1, 8(sp)
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    beqz a0, .LBB17_3
 ; RV32IF-NEXT:  # %bb.1: # %if.end
 ; RV32IF-NEXT:    mv a0, zero
-; RV32IF-NEXT:    jalr s1
+; RV32IF-NEXT:  .Ltmp18:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(dummy)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp18)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    flw ft1, 4(sp)
+; RV32IF-NEXT:    flw ft1, 8(sp)
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    beqz a0, .LBB17_3
 ; RV32IF-NEXT:  # %bb.2: # %if.end4
 ; RV32IF-NEXT:    mv a0, zero
-; RV32IF-NEXT:    lw s1, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB17_3: # %if.then
-; RV32IF-NEXT:    lui a0, %hi(abort)
-; RV32IF-NEXT:    addi a0, a0, %lo(abort)
-; RV32IF-NEXT:    jalr a0
+; RV32IF-NEXT:  .Ltmp19:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(abort)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp19)
 entry:
   %call = call float @dummy(float 0.000000e+00)
   %cmp = fcmp une float %call, 0.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   call void @abort()
   unreachable

test/CodeGen/RISCV/float-mem.ll

 
 define float @flw_stack(float %a) nounwind {
 ; RV32IF-LABEL: flw_stack:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    sw s1, 8(sp)
 ; RV32IF-NEXT:    mv s1, a0
-; RV32IF-NEXT:    lui a0, %hi(notdead)
-; RV32IF-NEXT:    addi a1, a0, %lo(notdead)
 ; RV32IF-NEXT:    addi a0, sp, 4
-; RV32IF-NEXT:    jalr a1
+; RV32IF-NEXT:  .Ltmp0:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32IF-NEXT:    fmv.w.x ft0, s1
 ; RV32IF-NEXT:    flw ft1, 4(sp)
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    lw s1, 8(sp)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret

 ; RV32IF-LABEL: fsw_stack:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fsw ft0, 8(sp)
-; RV32IF-NEXT:    lui a0, %hi(notdead)
-; RV32IF-NEXT:    addi a1, a0, %lo(notdead)
 ; RV32IF-NEXT:    addi a0, sp, 8
-; RV32IF-NEXT:    jalr a1
+; RV32IF-NEXT:  .Ltmp1:
+; RV32IF-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32IF-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
   %1 = fadd float %a, %b ; force store from FPR32
   %2 = alloca float, align 4
   store float %1, float* %2
   %3 = bitcast float* %2 to i8*
   call void @notdead(i8* %3)
   ret void
 }

test/CodeGen/RISCV/fp128.ll

 ; RV32I-NEXT:    lw a0, %lo(x+8)(a0)
 ; RV32I-NEXT:    sw a0, 32(sp)
 ; RV32I-NEXT:    lui a0, %hi(x+4)
 ; RV32I-NEXT:    lw a0, %lo(x+4)(a0)
 ; RV32I-NEXT:    sw a0, 28(sp)
 ; RV32I-NEXT:    lui a0, %hi(x)
 ; RV32I-NEXT:    lw a0, %lo(x)(a0)
 ; RV32I-NEXT:    sw a0, 24(sp)
-; RV32I-NEXT:    lui a0, %hi(__netf2)
-; RV32I-NEXT:    addi a2, a0, %lo(__netf2)
 ; RV32I-NEXT:    addi a0, sp, 24
 ; RV32I-NEXT:    addi a1, sp, 8
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__netf2)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    xor a0, a0, zero
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 44(sp)
 ; RV32I-NEXT:    addi sp, sp, 48
 ; RV32I-NEXT:    ret
   %1 = load fp128, fp128* @x, align 16
   %2 = load fp128, fp128* @y, align 16
   %cmp = fcmp une fp128 %1, %2

 ; RV32I-NEXT:    lw a0, %lo(x+8)(a0)
 ; RV32I-NEXT:    sw a0, 48(sp)
 ; RV32I-NEXT:    lui a0, %hi(x+4)
 ; RV32I-NEXT:    lw a0, %lo(x+4)(a0)
 ; RV32I-NEXT:    sw a0, 44(sp)
 ; RV32I-NEXT:    lui a0, %hi(x)
 ; RV32I-NEXT:    lw a0, %lo(x)(a0)
 ; RV32I-NEXT:    sw a0, 40(sp)
-; RV32I-NEXT:    lui a0, %hi(__addtf3)
-; RV32I-NEXT:    addi a3, a0, %lo(__addtf3)
 ; RV32I-NEXT:    addi a0, sp, 56
 ; RV32I-NEXT:    addi a1, sp, 40
 ; RV32I-NEXT:    addi a2, sp, 24
-; RV32I-NEXT:    jalr a3
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__addtf3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw a0, 68(sp)
 ; RV32I-NEXT:    sw a0, 20(sp)
 ; RV32I-NEXT:    lw a0, 64(sp)
 ; RV32I-NEXT:    sw a0, 16(sp)
 ; RV32I-NEXT:    lw a0, 60(sp)
 ; RV32I-NEXT:    sw a0, 12(sp)
 ; RV32I-NEXT:    lw a0, 56(sp)
 ; RV32I-NEXT:    sw a0, 8(sp)
-; RV32I-NEXT:    lui a0, %hi(__fixtfsi)
-; RV32I-NEXT:    addi a1, a0, %lo(__fixtfsi)
 ; RV32I-NEXT:    addi a0, sp, 8
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__fixtfsi)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    lw ra, 76(sp)
 ; RV32I-NEXT:    addi sp, sp, 80
 ; RV32I-NEXT:    ret
   %1 = load fp128, fp128* @x, align 16
   %2 = load fp128, fp128* @y, align 16
   %3 = fadd fp128 %1, %2
   %4 = fptosi fp128 %3 to i32
   ret i32 %4
 }

test/CodeGen/RISCV/frame.ll

 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 12(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 8(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(test1)
-; RV32I-FPELIM-NEXT:    addi a1, a0, %lo(test1)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 12
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp0:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(test1)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-FPELIM-NEXT:    mv a0, zero
 ; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -32
 ; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
 ; RV32I-WITHFP-NEXT:    sw zero, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -24(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -28(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -32(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(test1)
-; RV32I-WITHFP-NEXT:    addi a1, a0, %lo(test1)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -28
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp0:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(test1)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-WITHFP-NEXT:    mv a0, zero
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %key = alloca %struct.key_t, align 4
   %1 = bitcast %struct.key_t* %key to i8*
   call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 20, i1 false)
   %2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
   call void @test1(i8* %2) #3
   ret i32 0
 }
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
 
 declare void @test1(i8*)

test/CodeGen/RISCV/frameaddr-returnaddr.ll

 
 define i8* @test_frameaddress_3_alloca() nounwind {
 ; RV32I-LABEL: test_frameaddress_3_alloca:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -112
 ; RV32I-NEXT:    sw ra, 108(sp)
 ; RV32I-NEXT:    sw s0, 104(sp)
 ; RV32I-NEXT:    addi s0, sp, 112
-; RV32I-NEXT:    lui a0, %hi(notdead)
-; RV32I-NEXT:    addi a1, a0, %lo(notdead)
 ; RV32I-NEXT:    addi a0, s0, -108
-; RV32I-NEXT:    jalr a1
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw a0, -8(s0)
 ; RV32I-NEXT:    lw a0, -8(a0)
 ; RV32I-NEXT:    lw a0, -8(a0)
 ; RV32I-NEXT:    lw s0, 104(sp)
 ; RV32I-NEXT:    lw ra, 108(sp)
 ; RV32I-NEXT:    addi sp, sp, 112
 ; RV32I-NEXT:    ret
   %1 = alloca [100 x i8]

test/CodeGen/RISCV/init-array.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32-unknown-linux-gnu -verify-machineinstrs -o - %s \
 ; RUN: | FileCheck --check-prefix=INITARRAY %s
 ; RUN: llc -mtriple=riscv32-unknown-elf -verify-machineinstrs -o - %s \
 ; RUN: | FileCheck --check-prefix=INITARRAY %s
 ; RUN: llc -mtriple=riscv64-unknown-linux-gnu -verify-machineinstrs -o - %s \
 ; RUN: | FileCheck --check-prefix=INITARRAY %s
 ; RUN: llc -mtriple=riscv64-unknown-elf -verify-machineinstrs -o - %s \
 ; RUN: | FileCheck --check-prefix=INITARRAY %s
 
 ; RUN: llc -mtriple=riscv32-unknown-linux-gnu -verify-machineinstrs -use-ctors -o - %s \
 ; RUN: | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple=riscv32-unknown-elf -verify-machineinstrs -use-ctors -o - %s \
 ; RUN: | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple=riscv64-unknown-linux-gnu -verify-machineinstrs -use-ctors -o - %s \
 ; RUN: | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple=riscv64-unknown-elf -verify-machineinstrs -use-ctors -o - %s \
 ; RUN: | FileCheck --check-prefix=CTOR %s
 
 define internal void @_GLOBAL__I_a() section ".text.startup" {
+; INITARRAY-LABEL: _GLOBAL__I_a:
+; INITARRAY:       # %bb.0:
+; INITARRAY-NEXT:    ret
+;
+; CTOR-LABEL: _GLOBAL__I_a:
+; CTOR:       # %bb.0:
+; CTOR-NEXT:    ret
   ret void
 }
 
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
 
 ;INITARRAY: section .init_array
 ;INITARRAY-NOT: .section    .ctors
 
 ;CTOR: .section .ctors
 ;CTOR-NOT:  section .init_array
 

test/CodeGen/RISCV/mul.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @square(i32 %a) nounwind {
 ; RV32I-LABEL: square:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: square:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mul a0, a0, a0
 ; RV32IM-NEXT:    ret
   %1 = mul i32 %a, %a
   ret i32 %1
 }
 
 define i32 @mul(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: mul:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
 }
 
 define i32 @mul_constant(i32 %a) nounwind {
 ; RV32I-LABEL: mul_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    addi a1, zero, 5
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__mulsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi a1, zero, 5
 ; RV32IM-NEXT:    mul a0, a0, a1
; RV32IM-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @mul64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: mul64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a4, %hi(__muldi3)
-; RV32I-NEXT:    addi a4, a4, %lo(__muldi3)
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp3:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__muldi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mul a3, a0, a3
 ; RV32IM-NEXT:    mulhu a4, a0, a2
 ; RV32IM-NEXT:    add a3, a4, a3
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
   %1 = mul i64 %a, %b
   ret i64 %1
 }
 
 define i64 @mul64_constant(i64 %a) nounwind {
 ; RV32I-LABEL: mul64_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__muldi3)
-; RV32I-NEXT:    addi a4, a2, %lo(__muldi3)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp4:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__muldi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul64_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi a2, zero, 5
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
   %1 = mul i64 %a, 5
   ret i64 %1
 }
 
 define i32 @mulhs(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: mulhs:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, a1
-; RV32I-NEXT:    lui a1, %hi(__muldi3)
-; RV32I-NEXT:    addi a4, a1, %lo(__muldi3)
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    srai a3, a2, 31
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp5:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__muldi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mulhs:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mulh a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = sext i32 %a to i64
   %2 = sext i32 %b to i64
   %3 = mul i64 %1, %2
   %4 = lshr i64 %3, 32
   %5 = trunc i64 %4 to i32
   ret i32 %5
 }
 
 define i32 @mulhu(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: mulhu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, a1
-; RV32I-NEXT:    lui a1, %hi(__muldi3)
-; RV32I-NEXT:    addi a4, a1, %lo(__muldi3)
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    mv a3, zero
-; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:  .Ltmp6:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__muldi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mulhu:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mulhu a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = zext i32 %a to i64
   %2 = zext i32 %b to i64
   %3 = mul i64 %1, %2
   %4 = lshr i64 %3, 32
   %5 = trunc i64 %4 to i32
   ret i32 %5
 }

test/CodeGen/RISCV/rem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @urem(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: urem:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__umodsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__umodsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__umodsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: urem:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    remu a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
 }
 
 define i32 @srem(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: srem:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a2, %hi(__modsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__modsi3)
-; RV32I-NEXT:    jalr a2
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__modsi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: srem:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    rem a0, a0, a1
 ; RV32IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
 }

test/CodeGen/RISCV/shifts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; Basic shift support is tested as part of ALU.ll. This file ensures that
 ; shifts which may not be supported natively are lowered properly.
 
 define i64 @lshr64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: lshr64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a3, %hi(__lshrdi3)
-; RV32I-NEXT:    addi a3, a3, %lo(__lshrdi3)
-; RV32I-NEXT:    jalr a3
+; RV32I-NEXT:  .Ltmp0:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__lshrdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = lshr i64 %a, %b
   ret i64 %1
 }
 
 define i64 @ashr64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: ashr64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a3, %hi(__ashrdi3)
-; RV32I-NEXT:    addi a3, a3, %lo(__ashrdi3)
-; RV32I-NEXT:    jalr a3
+; RV32I-NEXT:  .Ltmp1:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__ashrdi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = ashr i64 %a, %b
   ret i64 %1
 }
 
 define i64 @shl64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: shl64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a3, %hi(__ashldi3)
-; RV32I-NEXT:    addi a3, a3, %lo(__ashldi3)
-; RV32I-NEXT:    jalr a3
+; RV32I-NEXT:  .Ltmp2:
+; RV32I-NEXT:    auipc ra, %pcrel_hi(__ashldi3)
+; RV32I-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
   %1 = shl i64 %a, %b
   ret i64 %1
 }

test/CodeGen/RISCV/vararg.ll

 ; RV32I-FPELIM-NEXT:    sw a2, 8(s0)
 ; RV32I-FPELIM-NEXT:    addi a0, s0, 8
 ; RV32I-FPELIM-NEXT:    sw a0, -16(s0)
 ; RV32I-FPELIM-NEXT:    lw s1, 4(s0)
 ; RV32I-FPELIM-NEXT:    addi a0, s1, 15
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -16
 ; RV32I-FPELIM-NEXT:    sub a0, sp, a0
 ; RV32I-FPELIM-NEXT:    mv sp, a0
-; RV32I-FPELIM-NEXT:    lui a1, %hi(notdead)
-; RV32I-FPELIM-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp0:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-FPELIM-NEXT:    mv a0, s1
 ; RV32I-FPELIM-NEXT:    addi sp, s0, -16
 ; RV32I-FPELIM-NEXT:    lw s1, 4(sp)
 ; RV32I-FPELIM-NEXT:    lw s0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32I-FPELIM-NEXT:    ret
 ;

 ; RV32I-WITHFP-NEXT:    sw a2, 8(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -16(s0)
 ; RV32I-WITHFP-NEXT:    lw s1, 4(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s1, 15
 ; RV32I-WITHFP-NEXT:    andi a0, a0, -16
 ; RV32I-WITHFP-NEXT:    sub a0, sp, a0
 ; RV32I-WITHFP-NEXT:    mv sp, a0
-; RV32I-WITHFP-NEXT:    lui a1, %hi(notdead)
-; RV32I-WITHFP-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp0:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp0)
 ; RV32I-WITHFP-NEXT:    mv a0, s1
 ; RV32I-WITHFP-NEXT:    addi sp, s0, -16
 ; RV32I-WITHFP-NEXT:    lw s1, 4(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %va = alloca i8*, align 4

 ; RV32I-NEXT:    ret
 ; Pass a double, as a float would be promoted by a C/C++ frontend
 ; RV32I-FPELIM-LABEL: va1_caller:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 261888
 ; RV32I-FPELIM-NEXT:    mv a3, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(va1)
-; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(va1)
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 2
 ; RV32I-FPELIM-NEXT:    mv a2, zero
-; RV32I-FPELIM-NEXT:    jalr a0
+; RV32I-FPELIM-NEXT:  .Ltmp1:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(va1)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va1_caller:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a0, 261888
 ; RV32I-WITHFP-NEXT:    mv a3, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(va1)
-; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(va1)
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 2
 ; RV32I-WITHFP-NEXT:    mv a2, zero
-; RV32I-WITHFP-NEXT:    jalr a0
+; RV32I-WITHFP-NEXT:  .Ltmp1:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(va1)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp1)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
   ret void
 }
 

 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ; RV32I-FPELIM-LABEL: va2_caller:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 261888
 ; RV32I-FPELIM-NEXT:    mv a3, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(va2)
-; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(va2)
 ; RV32I-FPELIM-NEXT:    mv a2, zero
-; RV32I-FPELIM-NEXT:    jalr a0
+; RV32I-FPELIM-NEXT:  .Ltmp2:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(va2)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va2_caller:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a0, 261888
 ; RV32I-WITHFP-NEXT:    mv a3, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(va2)
-; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(va2)
 ; RV32I-WITHFP-NEXT:    mv a2, zero
-; RV32I-WITHFP-NEXT:    jalr a0
+; RV32I-WITHFP-NEXT:  .Ltmp2:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(va2)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp2)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
  %1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
  ret void
 }
 

 ; RV32I-FPELIM-NEXT:    sw ra, 4(sp)
 ; RV32I-FPELIM-NEXT:    sw a7, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw a6, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw a5, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw a4, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw a3, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 27
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT:    addi a5, a0, %lo(__adddf3)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 19
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -8
 ; RV32I-FPELIM-NEXT:    lw a4, 0(a0)
 ; RV32I-FPELIM-NEXT:    ori a0, a0, 4
 ; RV32I-FPELIM-NEXT:    lw a3, 0(a0)
 ; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    mv a1, a2
 ; RV32I-FPELIM-NEXT:    mv a2, a4
-; RV32I-FPELIM-NEXT:    jalr a5
+; RV32I-FPELIM-NEXT:  .Ltmp3:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(__adddf3)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-FPELIM-NEXT:    lw ra, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va3:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -48
 ; RV32I-WITHFP-NEXT:    sw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 24
 ; RV32I-WITHFP-NEXT:    sw a7, 20(s0)
 ; RV32I-WITHFP-NEXT:    sw a6, 16(s0)
 ; RV32I-WITHFP-NEXT:    sw a5, 12(s0)
 ; RV32I-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, 4(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, 19
 ; RV32I-WITHFP-NEXT:    sw a0, -12(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT:    addi a5, a0, %lo(__adddf3)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, 11
 ; RV32I-WITHFP-NEXT:    andi a0, a0, -8
 ; RV32I-WITHFP-NEXT:    lw a4, 0(a0)
 ; RV32I-WITHFP-NEXT:    ori a0, a0, 4
 ; RV32I-WITHFP-NEXT:    lw a3, 0(a0)
 ; RV32I-WITHFP-NEXT:    mv a0, a1
 ; RV32I-WITHFP-NEXT:    mv a1, a2
 ; RV32I-WITHFP-NEXT:    mv a2, a4
-; RV32I-WITHFP-NEXT:    jalr a5
+; RV32I-WITHFP-NEXT:  .Ltmp3:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(__adddf3)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp3)
 ; RV32I-WITHFP-NEXT:    lw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %va = alloca i8*, align 4
   %1 = bitcast i8** %va to i8*
   call void @llvm.va_start(i8* %1)
   %2 = bitcast i8** %va to i32*

 ; RV32I-FPELIM-NEXT:    sw a3, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 19
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -8
 ; RV32I-FPELIM-NEXT:    ori a3, a0, 4
 ; RV32I-FPELIM-NEXT:    sw a3, 0(sp)
 ; RV32I-FPELIM-NEXT:    lw a4, 0(a0)
 ; RV32I-FPELIM-NEXT:    addi a0, a3, 4
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
-; RV32I-FPELIM-NEXT:    lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT:    addi a5, a0, %lo(__adddf3)
 ; RV32I-FPELIM-NEXT:    lw a3, 0(a3)
 ; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    mv a1, a2
 ; RV32I-FPELIM-NEXT:    mv a2, a4
-; RV32I-FPELIM-NEXT:    jalr a5
+; RV32I-FPELIM-NEXT:  .Ltmp4:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(__adddf3)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-FPELIM-NEXT:    lw ra, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va3_va_arg:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -48
 ; RV32I-WITHFP-NEXT:    sw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 24
 ; RV32I-WITHFP-NEXT:    sw a7, 20(s0)
 ; RV32I-WITHFP-NEXT:    sw a6, 16(s0)
 ; RV32I-WITHFP-NEXT:    sw a5, 12(s0)
 ; RV32I-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, 4(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, 11
 ; RV32I-WITHFP-NEXT:    andi a0, a0, -8
 ; RV32I-WITHFP-NEXT:    ori a3, a0, 4
 ; RV32I-WITHFP-NEXT:    sw a3, -12(s0)
 ; RV32I-WITHFP-NEXT:    lw a4, 0(a0)
 ; RV32I-WITHFP-NEXT:    addi a0, a3, 4
 ; RV32I-WITHFP-NEXT:    sw a0, -12(s0)
-; RV32I-WITHFP-NEXT:    lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT:    addi a5, a0, %lo(__adddf3)
 ; RV32I-WITHFP-NEXT:    lw a3, 0(a3)
 ; RV32I-WITHFP-NEXT:    mv a0, a1
 ; RV32I-WITHFP-NEXT:    mv a1, a2
 ; RV32I-WITHFP-NEXT:    mv a2, a4
-; RV32I-WITHFP-NEXT:    jalr a5
+; RV32I-WITHFP-NEXT:  .Ltmp4:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(__adddf3)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp4)
 ; RV32I-WITHFP-NEXT:    lw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %va = alloca i8*, align 4
   %1 = bitcast i8** %va to i8*
   call void @llvm.va_start(i8* %1)
   %2 = va_arg i8** %va, double

 ; RV32I-FPELIM-LABEL: va3_caller:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 261888
 ; RV32I-FPELIM-NEXT:    mv a2, a0
 ; RV32I-FPELIM-NEXT:    lui a0, 262144
 ; RV32I-FPELIM-NEXT:    mv a5, a0
-; RV32I-FPELIM-NEXT:    lui a0, %hi(va3)
-; RV32I-FPELIM-NEXT:    addi a3, a0, %lo(va3)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 2
 ; RV32I-FPELIM-NEXT:    mv a1, zero
 ; RV32I-FPELIM-NEXT:    mv a4, zero
-; RV32I-FPELIM-NEXT:    jalr a3
+; RV32I-FPELIM-NEXT:  .Ltmp5:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(va3)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va3_caller:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a0, 261888
 ; RV32I-WITHFP-NEXT:    mv a2, a0
 ; RV32I-WITHFP-NEXT:    lui a0, 262144
 ; RV32I-WITHFP-NEXT:    mv a5, a0
-; RV32I-WITHFP-NEXT:    lui a0, %hi(va3)
-; RV32I-WITHFP-NEXT:    addi a3, a0, %lo(va3)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 2
 ; RV32I-WITHFP-NEXT:    mv a1, zero
 ; RV32I-WITHFP-NEXT:    mv a4, zero
-; RV32I-WITHFP-NEXT:    jalr a3
+; RV32I-WITHFP-NEXT:  .Ltmp5:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(va3)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp5)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
  %1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
  ret void
 }
 

 ; RV32I-FPELIM-NEXT:    sw a5, 36(sp)
 ; RV32I-FPELIM-NEXT:    sw a4, 32(sp)
 ; RV32I-FPELIM-NEXT:    sw a3, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw a2, 24(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 24
 ; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lw s1, 20(sp)
-; RV32I-FPELIM-NEXT:    lui a1, %hi(notdead)
-; RV32I-FPELIM-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-FPELIM-NEXT:    jalr a1
+; RV32I-FPELIM-NEXT:  .Ltmp6:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-FPELIM-NEXT:    lw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 3
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -4
 ; RV32I-FPELIM-NEXT:    addi a1, a0, 4
 ; RV32I-FPELIM-NEXT:    sw a1, 4(sp)
 ; RV32I-FPELIM-NEXT:    lw a1, 0(a0)
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 7
 ; RV32I-FPELIM-NEXT:    andi a0, a0, -4

 ; RV32I-WITHFP-NEXT:    sw a5, 20(s0)
 ; RV32I-WITHFP-NEXT:    sw a4, 16(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, 12(s0)
 ; RV32I-WITHFP-NEXT:    sw a2, 8(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw a0, -20(s0)
 ; RV32I-WITHFP-NEXT:    lw s1, 4(s0)
-; RV32I-WITHFP-NEXT:    lui a1, %hi(notdead)
-; RV32I-WITHFP-NEXT:    addi a1, a1, %lo(notdead)
-; RV32I-WITHFP-NEXT:    jalr a1
+; RV32I-WITHFP-NEXT:  .Ltmp6:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(notdead)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp6)
 ; RV32I-WITHFP-NEXT:    lw a0, -16(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 3
 ; RV32I-WITHFP-NEXT:    andi a0, a0, -4
 ; RV32I-WITHFP-NEXT:    addi a1, a0, 4
 ; RV32I-WITHFP-NEXT:    sw a1, -16(s0)
 ; RV32I-WITHFP-NEXT:    lw a1, 0(a0)
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 7
 ; RV32I-WITHFP-NEXT:    andi a0, a0, -4

 ; RV32I-FPELIM-NEXT:    lui a0, 964690
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -328
 ; RV32I-FPELIM-NEXT:    sw a0, 36(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a6, a0, -2048
-; RV32I-FPELIM-NEXT:    lui a0, %hi(va5_aligned_stack_callee)
-; RV32I-FPELIM-NEXT:    addi a5, a0, %lo(va5_aligned_stack_callee)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 4
-; RV32I-FPELIM-NEXT:    jalr a5
+; RV32I-FPELIM-NEXT:  .Ltmp7:
+; RV32I-FPELIM-NEXT:    auipc ra, %pcrel_hi(va5_aligned_stack_callee)
+; RV32I-FPELIM-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 64
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: va5_aligned_stack_caller:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -64
 ; RV32I-WITHFP-NEXT:    sw ra, 60(sp)

 ; RV32I-WITHFP-NEXT:    lui a0, 964690
 ; RV32I-WITHFP-NEXT:    addi a0, a0, -328
 ; RV32I-WITHFP-NEXT:    sw a0, -28(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 335544
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 1311
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, 688509
 ; RV32I-WITHFP-NEXT:    addi a6, a0, -2048
-; RV32I-WITHFP-NEXT:    lui a0, %hi(va5_aligned_stack_callee)
-; RV32I-WITHFP-NEXT:    addi a5, a0, %lo(va5_aligned_stack_callee)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 4
-; RV32I-WITHFP-NEXT:    jalr a5
+; RV32I-WITHFP-NEXT:  .Ltmp7:
+; RV32I-WITHFP-NEXT:    auipc ra, %pcrel_hi(va5_aligned_stack_callee)
+; RV32I-WITHFP-NEXT:    jalr ra, ra, %pcrel_lo(.Ltmp7)
 ; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 64
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
     i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
   ret void