This adds support in the RISCVAsmParser the storing of Subtarget feature bits to a stack so that they can be pushed/popped to enable/disable multiple features at once.
Could you please expand the test to verify push+pop works for a pair of options (rvc+relax)? Passing -riscv-no-aliases should let you check whether a compressed instruction was produced or not.
A couple of minor comments but otherwise looks good to my non-authoritative eyes.
|136 ↗||(On Diff #170179)|
Missing blank line after this
|1325 ↗||(On Diff #170179)|
You use StartLoc here but manually call Parser.geTok().getLoc() earlier. Personally I'd just remove StartLoc altogether, it's only required on the error paths and only ever used once on each path.
Thanks Lewis, this looks good to me - just a couple of very minor requested tweaks noted inline.
|128 ↗||(On Diff #170897)|
if (FeatureBitStack.empty()) would be a ever so slightly more readable.
|131 ↗||(On Diff #170897)|
LLVM is quite conservative about the use of auto, though this isn't always adhered to throughout LLVM https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable. Might be worth using an explicit type here.
|18 ↗||(On Diff #170897)|
Can you add tests for .option push and .option pop with extra tokens at the end of the input? e.g. .option pop 2?