[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced

[shiva0217]

Summary

For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed.

We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved.

To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true.

RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced).

RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer.

The patch is based on the discussion in https://reviews.llvm.org/D44887.

[asb]

This looks good to me, thanks!

llvm/trunk/include/llvm/MC/MCAsmBackend.h

public:
   /// \param Inst - The instruction to test.
   virtual bool mayNeedRelaxation(const MCInst &Inst) const = 0;
 
   /// Target specific predicate for whether a given fixup requires the
   /// associated instruction to be relaxed.
   virtual bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
                                             uint64_t Value,
                                             const MCRelaxableFragment *DF,
-                                            const MCAsmLayout &Layout) const;
+                                            const MCAsmLayout &Layout,
+                                            const bool WasForced) const;
 
   /// Simple predicate for targets where !Resolved implies requiring relaxation
   virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                     const MCRelaxableFragment *DF,
                                     const MCAsmLayout &Layout) const = 0;
 
   /// Relax the instruction in the given fragment to the next wider instruction.
   ///

llvm/trunk/include/llvm/MC/MCAssembler.h

private:
   ///
   /// \param Layout The layout to use for evaluation.
   /// \param Fixup The fixup to evaluate.
   /// \param DF The fragment the fixup is inside.
   /// \param Target [out] On return, the relocatable expression the fixup
   /// evaluates to.
   /// \param Value [out] On return, the value of the fixup as currently laid
   /// out.
+  /// \param WasForced [out] On return, the value in the fixup is set to the
+  /// correct value if WasForced is true, even if evaluateFixup returns false.
   /// \return Whether the fixup value was fully resolved. This is true if the
   /// \p Value result is fixed, otherwise the value may change due to
   /// relocation.
   bool evaluateFixup(const MCAsmLayout &Layout, const MCFixup &Fixup,
                      const MCFragment *DF, MCValue &Target,
-                     uint64_t &Value) const;
+                     uint64_t &Value, bool &WasForced) const;
 
   /// Check whether a fixup can be satisfied, or whether it needs to be relaxed
   /// (increased in size, in order to hold its value correctly).
   bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const;
 
   /// Check whether the given fragment needs relaxation.
   bool fragmentNeedsRelaxation(const MCRelaxableFragment *IF,

llvm/trunk/lib/MC/MCAsmBackend.cpp

static const MCFixupKindInfo Builtins[] = {
       {"FK_SecRel_8", 0, 64, 0}};
 
   assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind");
   return Builtins[Kind];
 }
 
 bool MCAsmBackend::fixupNeedsRelaxationAdvanced(
     const MCFixup &Fixup, bool Resolved, uint64_t Value,
-    const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const {
+    const MCRelaxableFragment *DF, const MCAsmLayout &Layout,
+    const bool WasForced) const {
   if (!Resolved)
     return true;
   return fixupNeedsRelaxation(Fixup, Value, DF, Layout);
 }
 
 void MCAsmBackend::handleCodePaddingBasicBlockStart(
     MCObjectStreamer *OS, const MCCodePaddingContext &Context) {
   CodePadder->handleBasicBlockStart(OS, Context);

 }
 
 void MCAsmBackend::handleCodePaddingInstructionEnd(const MCInst &Inst) {
   CodePadder->handleInstructionEnd(Inst);
 }
 
 bool MCAsmBackend::relaxFragment(MCPaddingFragment *PF, MCAsmLayout &Layout) {
   return CodePadder->relaxFragment(PF, Layout);
-}
+}
 

llvm/trunk/lib/MC/MCAssembler.cpp

if (!getContext().getAsmInfo()->isSectionAtomizableBySymbols(
     return nullptr;
 
   // Otherwise, return the atom for the containing fragment.
   return S.getFragment()->getAtom();
 }
 
 bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout,
                                 const MCFixup &Fixup, const MCFragment *DF,
-                                MCValue &Target, uint64_t &Value) const {
+                                MCValue &Target, uint64_t &Value,
+                                bool &WasForced) const {
   ++stats::evaluateFixup;
 
   // FIXME: This code has some duplication with recordRelocation. We should
   // probably merge the two into a single callback that tries to evaluate a
   // fixup and records a relocation if one is needed.
 
   // On error claim to have completely evaluated the fixup, to prevent any
   // further processing from being done.
   const MCExpr *Expr = Fixup.getValue();
   MCContext &Ctx = getContext();
   Value = 0;
+  WasForced = false;
   if (!Expr->evaluateAsRelocatable(Target, &Layout, &Fixup)) {
     Ctx.reportError(Fixup.getLoc(), "expected relocatable expression");
     return true;
   }
   if (const MCSymbolRefExpr *RefB = Target.getSymB()) {
     if (RefB->getKind() != MCSymbolRefExpr::VK_None) {
       Ctx.reportError(Fixup.getLoc(),
                       "unsupported subtraction of qualified symbol");
if (IsPCRel) {
 
     // A number of ARM fixups in Thumb mode require that the effective PC
     // address be determined as the 32-bit aligned version of the actual offset.
     if (ShouldAlignPC) Offset &= ~0x3;
     Value -= Offset;
   }
 
   // Let the backend force a relocation if needed.
-  if (IsResolved && getBackend().shouldForceRelocation(*this, Fixup, Target))
+  if (IsResolved && getBackend().shouldForceRelocation(*this, Fixup, Target)) {
     IsResolved = false;
+    WasForced = true;
+  }
 
   return IsResolved;
 }
 
 uint64_t MCAssembler::computeFragmentSize(const MCAsmLayout &Layout,
                                           const MCFragment &F) const {
   assert(getBackendPtr() && "Requires assembler backend");
   switch (F.getKind()) {

 }
 
 std::tuple<MCValue, uint64_t, bool>
 MCAssembler::handleFixup(const MCAsmLayout &Layout, MCFragment &F,
                          const MCFixup &Fixup) {
   // Evaluate the fixup.
   MCValue Target;
   uint64_t FixedValue;
-  bool IsResolved = evaluateFixup(Layout, Fixup, &F, Target, FixedValue);
+  bool WasForced;
+  bool IsResolved = evaluateFixup(Layout, Fixup, &F, Target, FixedValue,
+                                  WasForced);
   if (!IsResolved) {
     // The fixup was unresolved, we need a relocation. Inform the object
     // writer of the relocation, and give it an opportunity to adjust the
     // fixup value if need be.
     getWriter().recordRelocation(*this, Layout, &F, Fixup, Target, FixedValue);
   }
   return std::make_tuple(Target, FixedValue, IsResolved);
 }

 }
 
 bool MCAssembler::fixupNeedsRelaxation(const MCFixup &Fixup,
                                        const MCRelaxableFragment *DF,
                                        const MCAsmLayout &Layout) const {
   assert(getBackendPtr() && "Expected assembler backend");
   MCValue Target;
   uint64_t Value;
-  bool Resolved = evaluateFixup(Layout, Fixup, DF, Target, Value);
+  bool WasForced;
+  bool Resolved = evaluateFixup(Layout, Fixup, DF, Target, Value, WasForced);
   if (Target.getSymA() &&
       Target.getSymA()->getKind() == MCSymbolRefExpr::VK_X86_ABS8 &&
       Fixup.getKind() == FK_Data_1)
     return false;
   return getBackend().fixupNeedsRelaxationAdvanced(Fixup, Resolved, Value, DF,
-                                                   Layout);
+                                                   Layout, WasForced);
 }
 
 bool MCAssembler::fragmentNeedsRelaxation(const MCRelaxableFragment *F,
                                           const MCAsmLayout &Layout) const {
   assert(getBackendPtr() && "Expected assembler backend");
   // If this inst doesn't ever need relaxation, ignore it. This occurs when we
   // are intentionally pushing out inst fragments, or because we relaxed a
   // previous instruction to one that doesn't need relaxation.

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

bool mayNeedRelaxation(MCInst const &Inst) const override {
     return true;
   }
 
   /// fixupNeedsRelaxation - Target specific predicate for whether a given
   /// fixup requires the associated instruction to be relaxed.
   bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
                                     uint64_t Value,
                                     const MCRelaxableFragment *DF,
-                                    const MCAsmLayout &Layout) const override {
+                                    const MCAsmLayout &Layout,
+                                    const bool WasForced) const override {
     MCInst const &MCB = DF->getInst();
     assert(HexagonMCInstrInfo::isBundle(MCB));
 
     *RelaxTarget = nullptr;
     MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
         MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
     bool Relaxable = isInstRelaxable(MCI);
     if (Relaxable == false)

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

public:
   // during relaxation.
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override {
     return STI.getFeatureBits()[RISCV::FeatureRelax];
   }
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const override;
+                            const MCAsmLayout &Layout) const override {
+    llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
+  }
+
+  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
+                                    uint64_t Value,
+                                    const MCRelaxableFragment *DF,
+                                    const MCAsmLayout &Layout,
+                                    const bool WasForced) const override;
 
   unsigned getNumFixupKinds() const override {
     return RISCV::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
public:
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
 
   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 };
 
 
-bool RISCVAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
+bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
+                                                   bool Resolved,
                                                    uint64_t Value,
                                                    const MCRelaxableFragment *DF,
-                                           const MCAsmLayout &Layout) const {
+                                                   const MCAsmLayout &Layout,
+                                                   const bool WasForced) const {
+  // Return true if the symbol is actually unresolved.
+  // Resolved could be always false when shouldForceRelocation return true.
+  // We use !WasForced to indicate that the symbol is unresolved and not forced
+  // by shouldForceRelocation.
+  if (!Resolved && !WasForced)
+    return true;
+
   int64_t Offset = int64_t(Value);
   switch ((unsigned)Fixup.getKind()) {
   default:
     return false;
   case RISCV::fixup_riscv_rvc_branch:
     // For compressed branch instructions the immediate must be
     // in the range [-256, 254].
     return Offset > 254 || Offset < -256;

llvm/trunk/test/MC/RISCV/compressed-relocations.s

 # RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \
 # RUN:     | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 
 # Check prefixes:
 # RELOC - Check the relocation in the object.
 # FIXUP - Check the fixup on the instruction.
 # INSTR - Check the instruction is handled properly by the ASMPrinter
 c.jal foo
 # A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
 # RELOC: R_RISCV_JAL
 # INSTR: c.jal foo
 # FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_jump
 
 c.bnez a0, foo
 # A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez).
 # RELOC: R_RISCV_BRANCH
 # INSTR: c.bnez a0, foo
 # FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_branch

llvm/trunk/test/MC/RISCV/rv32-relaxation.s

 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
 # RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=RELAX-INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
 
 FAR_JUMP_NEGATIVE:
   c.nop
 .space 2000
 
 FAR_BRANCH_NEGATIVE:
   c.nop
 .space 256
 
 NEAR_NEGATIVE:
   c.nop
 
 start:
   c.bnez a0, NEAR
 #INSTR: c.bnez a0, 72
+#RELAX-INSTR: c.bnez a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, NEAR_NEGATIVE
 #INSTR: c.bnez a0, -4
+#RELAX-INSTR: c.bnez a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, FAR_BRANCH
 #INSTR-NEXT: bne a0, zero, 326
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: bne a0, zero, -268
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP
 #INSTR-NEXT: bne a0, zero, 2320
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP_NEGATIVE
 #INSTR-NEXT: bne a0, zero, -2278
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
 
   c.beqz a0, NEAR
 #INSTR-NEXT: c.beqz a0, 52
+#RELAX-INSTR-NEXT: c.beqz a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, NEAR_NEGATIVE
 #INSTR-NEXT: c.beqz a0, -24
+#RELAX-INSTR-NEXT: c.beqz a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, FAR_BRANCH
 #INSTR-NEXT: beq a0, zero, 306
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: beq a0, zero, -288
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP
 #INSTR-NEXT: beq a0, zero, 2300
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP_NEGATIVE
 #INSTR-NEXT: beq a0, zero, -2298
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
 
   c.j NEAR
 #INSTR-NEXT: c.j 32
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j NEAR_NEGATIVE
 #INSTR-NEXT: c.j -44
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH
 #INSTR-NEXT: c.j 286
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.j -306
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_JUMP
 #INSTR-NEXT: jal zero, 2284
+#RELAX-INSTR-NEXT: jal zero, 0
+#RELAX-RELOC: R_RISCV_JAL
   c.j FAR_JUMP_NEGATIVE
 #INSTR-NEXT: jal zero, -2314
+#RELAX-INSTR-NEXT: jal zero, 0
+#RELAX-RELOC: R_RISCV_JAL
 
   c.jal NEAR
 #INSTR: c.jal 16
+#RELAX-INSTR: c.jal 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal NEAR_NEGATIVE
 #INSTR: c.jal -60
+#RELAX-INSTR: c.jal 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_BRANCH
 #INSTR-NEXT: c.jal 270
+#RELAX-INSTR-NEXT: c.jal 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.jal -322
+#RELAX-INSTR-NEXT: c.jal 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_JUMP
 #INSTR-NEXT: jal ra, 2268
+#RELAX-INSTR-NEXT: jal ra, 0
+#RELAX-RELOC: R_RISCV_JAL
   c.jal FAR_JUMP_NEGATIVE
 #INSTR-NEXT: jal ra, -2330
+#RELAX-INSTR-NEXT: jal ra, 0
+#RELAX-RELOC: R_RISCV_JAL
 
 NEAR:
   c.nop
 .space 256
 FAR_BRANCH:
   c.nop
 .space 2000
 FAR_JUMP:
   c.nop

llvm/trunk/test/MC/RISCV/rv64-relaxation.s

 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
 # RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=RELAX-INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
 
 FAR_JUMP_NEGATIVE:
   c.nop
 .space 2000
 
 FAR_BRANCH_NEGATIVE:
   c.nop
 .space 256
 
 NEAR_NEGATIVE:
   c.nop
 
 start:
   c.bnez a0, NEAR
 #INSTR: c.bnez a0, 56
+#RELAX-INSTR: c.bnez a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, NEAR_NEGATIVE
 #INSTR: c.bnez a0, -4
+#RELAX-INSTR: c.bnez a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, FAR_BRANCH
 #INSTR-NEXT: bne a0, zero, 310
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: bne a0, zero, -268
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP
 #INSTR-NEXT: bne a0, zero, 2304
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP_NEGATIVE
 #INSTR-NEXT: bne a0, zero, -2278
+#RELAX-INSTR-NEXT: bne a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
 
   c.beqz a0, NEAR
 #INSTR-NEXT: c.beqz a0, 36
+#RELAX-INSTR-NEXT: c.beqz a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, NEAR_NEGATIVE
 #INSTR-NEXT: c.beqz a0, -24
+#RELAX-INSTR-NEXT: c.beqz a0, 0
+#RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, FAR_BRANCH
 #INSTR-NEXT: beq a0, zero, 290
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: beq a0, zero, -288
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP
 #INSTR-NEXT: beq a0, zero, 2284
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP_NEGATIVE
 #INSTR-NEXT: beq a0, zero, -2298
+#RELAX-INSTR-NEXT: beq a0, zero, 0
+#RELAX-RELOC: R_RISCV_BRANCH
 
   c.j NEAR
 #INSTR-NEXT: c.j 16
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j NEAR_NEGATIVE
 #INSTR-NEXT: c.j -44
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH
 #INSTR-NEXT: c.j 270
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.j -306
+#RELAX-INSTR-NEXT: c.j 0
+#RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_JUMP
 #INSTR-NEXT: jal zero, 2268
+#RELAX-INSTR-NEXT: jal zero, 0
+#RELAX-RELOC: R_RISCV_JAL
   c.j FAR_JUMP_NEGATIVE
 #INSTR-NEXT: jal zero, -2314
+#RELAX-INSTR-NEXT: jal zero, 0
+#RELAX-RELOC: R_RISCV_JAL
 
 NEAR:
   c.nop
 
 .space 256
 FAR_BRANCH:
   c.nop
 
 .space 2000
 FAR_JUMP:
   c.nop