[AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands

[sdesmalen]

Summary

Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand.

Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE.

[fhahn]

LGTM, / should only be valid for SVE predicates. I think it should be also fine for the Apple Asm variant, but I am adding @MatzeB and @t.p.northover as reviewers in case I am missing something.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

2832

nit: No need for a variable here.

lib/Target/AArch64/AArch64.td

 //===----------------------------------------------------------------------===//
 // Assembly parser
 //===----------------------------------------------------------------------===//
 
 def GenericAsmParserVariant : AsmParserVariant {
   int Variant = 0;
   string Name = "generic";
   string BreakCharacters = ".";
+  string TokenizingCharacters = "[]*!/";
 }
 
 def AppleAsmParserVariant : AsmParserVariant {
   int Variant = 1;
   string Name = "apple-neon";
   string BreakCharacters = ".";
+  string TokenizingCharacters = "[]*!/";
 }
 
 //===----------------------------------------------------------------------===//
 // Assembly printer
 //===----------------------------------------------------------------------===//
 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 // AsmWriter bits get associated with the correct class.
 def GenericAsmWriter : AsmWriter {

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
 
   if (!ElementWidth)
     return MatchOperand_NoMatch;
 
   Operands.push_back(
       AArch64Operand::CreateReg(RegNum, RegKind::SVEPredicateVector,
                                 ElementWidth, S, getLoc(), getContext()));
 
+  // Not all predicates are followed by a '/m' or '/z'.
+  MCAsmParser &Parser = getParser();
+  if (Parser.getTok().isNot(AsmToken::Slash))
+    return MatchOperand_Success;
+
+  // But when they do they shouldn't have an element type suffix.
+  if (!Kind.empty()) {
+    Error(S, "not expecting size suffix");
+    return MatchOperand_ParseFail;
+  }
+
+  // Add a literal slash as operand
+  Operands.push_back(
+      AArch64Operand::CreateToken("/" , false, getLoc(), getContext()));
+
+  Parser.Lex(); // Eat the slash.
+
+  // Zeroing or merging?
+  StringRef Pred = Parser.getTok().getString().lower();
+  if (Pred != "z" && Pred != "m") {
+    Error(getLoc(), "expecting 'm' or 'z' predication");
+    return MatchOperand_ParseFail;
+  }
+
+  // Add zero/merge token.
+  const char *ZM = Pred == "z" ? "z" : "m";
+  Operands.push_back(
+    AArch64Operand::CreateToken(ZM, false, getLoc(), getContext()));
+
+  Parser.Lex(); // Eat zero/merge token.
   return MatchOperand_Success;
 }
 
 /// parseRegister - Parse a non-vector register operand.
 bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
   SMLoc S = getLoc();
   // Try for a vector (neon) register.
   if (!tryParseNeonVectorRegister(Operands))