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[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

Authored by sdesmalen on Dec 20 2017, 6:27 AM.



Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)

Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.

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Event Timeline

sdesmalen created this revision.Dec 20 2017, 6:27 AM

Looks reasonable to me. Adding a couple of more people who might have additional suggestions.

javed.absar added inline comments.Jan 2 2018, 2:23 AM

Looks like some code duplication between PPR and PPR_3b could be factored out by creating an intermediate class. You may want to consider it.

sdesmalen updated this revision to Diff 128415.Jan 2 2018, 6:42 AM

Removed some code duplication around PPR and PPR_3b register classes.

sdesmalen added inline comments.Jan 2 2018, 6:43 AM

Thanks for the suggestion @javed.absar , I've updated the patch.

fhahn accepted this revision.Jan 2 2018, 9:09 AM

LGTM. Thanks Javed & Sander

This revision is now accepted and ready to land.Jan 2 2018, 9:09 AM
sdesmalen closed this revision.Jan 3 2018, 2:16 AM