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[AArch64][SVE] Asm: Add predicated ADD/SUB instructions
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Authored by sdesmalen on Dec 20 2017, 6:27 AM.

Details

Summary

Add the predicated ADD/SUB instructions and corresponding tests.

Patch [3/3] in a series to add predicated ADD/SUB instructions for SVE.

Diff Detail

Event Timeline

sdesmalen created this revision.Dec 20 2017, 6:27 AM
fhahn added inline comments.Jan 8 2018, 6:04 AM
lib/Target/AArch64/AArch64SVEInstrInfo.td
18

It takes 4 registers, shouldn't the name be ADD_ZPmZZ? Same below

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
94–96

No need for llvm:: here.

test/MC/AArch64/SVE/add-diagnostics.s
21

IIRC you changed the comment/grouping structure in a previous patch. Could you use the same here?

// Comment about case
add 8bit,
add a16bit,
...
...

sdesmalen updated this revision to Diff 128934.Jan 8 2018, 8:06 AM

Reformatted diagnostics tests.

sdesmalen marked 2 inline comments as done.Jan 8 2018, 8:07 AM
sdesmalen added inline comments.
lib/Target/AArch64/AArch64SVEInstrInfo.td
18

This is done to distinguish it from cases where the first input register is not tied with the destination register, but also takes 4 registers, e.g. 'FMLA_ZPmZZ'.

fhahn accepted this revision.Jan 8 2018, 8:21 AM

Thanks Sander, LGTM

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
95

Looks like RegNo now could fit on the previous line ;-)

This revision is now accepted and ready to land.Jan 8 2018, 8:21 AM
sdesmalen closed this revision.Jan 9 2018, 4:44 AM