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[AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate…

Description

[AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands

Summary:
Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand.

Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover

Reviewed By: fhahn

Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D41442

Details

Committed
s.desmalenJan 9 2018, 3:17 AM
Reviewer
fhahn
Differential Revision
D41442: [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands
Parents
rL322069: [Nios2] Arithmetic instructions for R1 and R2 ISA.
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