[RISCV 10/10] Add common fixups and relocations

[asb]

Summary

%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type).

Additionally, fixups and relocations in jal and branch instructions are supported.

I actually tried a couple ways of handling this and decided that introspecting the instruction format in RISCVMCCodeEmitter ended up cleanest. I'd be happy to hear any other suggestions though.

This completes the first batch of patches.

[asb]

Refresh patch to reflect changes made in earlier patches in the series.

[asb]

Refresh patch to reflect changes earlier in the series.

[asb]

Update test style as suggested by @jyknight in D23564

[Razer6]

@theraven @jyknight What's the state of this change?

[theraven]

In D23568#663066, @Razer6 wrote:

@theraven @jyknight What's the state of this change?

The patch looks fine to me, but I thought it was waiting on the RISC-V ABI document discussing relocation in more detail than 'go see what binutils does'.

[asb]

In D23568#663066, @Razer6 wrote:

@theraven @jyknight What's the state of this change?

There has been progress on documenting aspects of the RISC-V ABI, though I decided to hold off on pushing for finalising the second half of my initial patchset due to concerns some parts of it may change with the addition of codegen support. I've lost more time than I expected to due to travel, other development responsibilities, and trying to secure further funding so I'm a little behind where I expected to be in terms of the codegen patches but I will put them up for review either over the weekend or next week, and also refresh these patches.

[asb]

This refresh adds support for relocations and fixups on branch and jal instructions. This is sufficient for compiling simple programs.

The intent is this patch is now ready for merging.

[asb]

Here's the same patch as before with full context, apologies for the noise.

[asb]

This updated version of the patch reflects upstream changes to arguments of applyFixup, and takes advantage of my work in rL299529 to report errors for out-of-range or insufficiently aligned fixups.

[majnemer]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

561–565

This would be more clear as:

// It's a simple symbol reference with no addend.
if (isa<MCSymbolRefExpr>(Expr))
  return true;

564

Is it your intention to return true with Kind equal to RISCVMCExpr::VK_RISCV_Invalid?

586

Didn't your just isa<>? I think this can be cast<>.

[asb]

Updated to address @majnemer's review comments (thanks!).

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

564

It's not, good catch. Initialising Kind to RISCVMCExpr::VK_RISCV_None seems to be the correct thing to do.

586

I think this is the first time we check for MCConstantExpr. Unless I'm misunderstanding you, I don't think this has to be a dyn_cast

[dylanmckay]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

11

This is not in alphabetical order

420

redundant break

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

42

Do you need this cast here? You save a similar switch in RISCVAsmBackend without one

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

168

Nitpick: The double nesting and duplicating of the unreachable isn't that intuitive - we might be able to simplify the control flow by initialising FixupKind to a sentinel value, dropping both else { unreachable } blocks, and then just placing a if (FixupKind == sentinel) { unreachable }

[asb]

Address review comments from @dylanmckay (thanks!).

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

42

The cast is needed to avoid a warning "case value not in enumerated type 'llvm::MCFixupKind'".

[dylanmckay]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

169

No else after return

183

Can we factor any code out from both isSImm13Lsb0 and the other signed immediated lsb functions? It seems like the only difference in these functions are the sizes of the immediates

If the same could be done for the UImm functions, that'd be good, although a quick glance shows that there is some differing logic based on the variant

186

No else after return

197

No else after return

210

No else after return

273

Is there a reason why this is only executed for RISCVMCExpr objects? AFAIK, evaluateAsConstant is also supported by MCExpr, and so I'm not sure if you're intentionally not evaluating those expressions here.

477

Should this be getIdentifier()?

It seems strange that you'd verify that the token is an identifier in the above if, but then read a string instead.

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

36

I don't think we want a full stop here because it might muck up the output of llc --stats, or at least make it look funny

[asb]

Thanks for the comments Dylan. Playing around with this, I've noticed that the MC assembler is too accepting of some inputs (e.g. accepting addi a1, a2, %hi(foo) where gas would reject it). I'm fixing this and expanding tests now, which will change many of the isFoo functions anyway. I'll watch for the else after return thing. I personally don't find that guideline very compelling for else if cases where removing the else fails to reduce indentation, but I shall of course conform with LLVM norms :)

The last patch update didn't have full context included - sorry for that.

[dylanmckay]

No problem, I remember it being quite hard to merge my own backend in-tree due to reviewers being scarce, thought I might as well help out :)

I personally don't find that guideline very compelling for else if in cases where removing the else fails to reduce indentation

I can definitely understand that, at first I thought that the no else after return rule only applied to else, but I checked before this review and was surprised as well.

The last patch update didn't have full context included - sorry for that.

No problem - that reminds me that I just made the same mistake on a patchset I just created!

[asb]

Previous versions of this patch were too accepting of invalid inputs, e.g. accepting addi a0, a0, %hi(1). Previously there was logic that would try to evaluate a RISCVMCExpr as a constant in createImm (i.e. as early as possible). This throws away information about any operand modifier that was parsed. Therefore, move to evaluating the constant in in the isFoo() predicate arguments, which also checks whether any operand modifiers were allowed. rv32i-invalid.s has been expanded to systematically test these issues. As suggested by Dylan, I've also added a helper function to factor out the commonality between the isSImmNNLsb0 functions.

[asb]

Just spotted a minor issue. RISCVMCExpr::getVariantKindForName would be better returning VK_RISCV_Invalid if the name is unrecognised rather htna VK_RISCV_None. Updated diff fixes this.

[asb]

Ping?

[mgrang]

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

66

Extra newline?

136

Do we really need to use another variable Idx? Can't we simply use i?

lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp

69

Default should be the first case in a switch.

97

Ditto.

[asb]

Update to address review comments (thanks @mgrang!).

[asb]

Refresh patch based on updates to others in series.

@dylanmckay, are you happy with this now?

[sabuasal]

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

148 ↗

(On Diff #116941)

I think this is problematic, fixup_riscv_lo12_i is only used for S instruction format in RISCV. I think this should be
if (MIFrom == RISCVII::InstFormatI) {

FixUpKind = RISCV::fixup_riscv_lo12_i;

} else if (RISCVII::InstFormatS) {
FixUpKind = RISCV::fixup_riscv_lo12_s;
} else {

llvm_unreacable("unexpected Instructio type for relocation  FixUpKind = RISCV::fixup_riscv_lo12_i");

}

Other wise you'll mistakenly end up generating instructions instructions with wrong fixup kinds!

[sabuasal]

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

148 ↗

(On Diff #116941)

correction: *fixup_riscv_lo12_s* is only used for S instruction format in RISCV.

[asb]

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

148 ↗

(On Diff #116941)

You're right this code path isn't written very defensively, and it may start to fail if VK_RISCV_LO is used with different instruction formats. I've addressed this in rL325775. Thanks for spotting this.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "MCTargetDesc/RISCVMCExpr.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCExpr.h"

 
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
 #include "RISCVGenAsmMatcher.inc"
 
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
   OperandMatchResultTy parseRegister(OperandVector &Operands);
   OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
+  OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands);
 
 public:
   enum RISCVMatchResultTy {
     Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "RISCVGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
   };
 
+  static bool classifySymbolRef(const MCExpr *Expr,
+                                RISCVMCExpr::VariantKind &Kind,
+                                int64_t &Addend);
+
   RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                  const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI), Parser(Parser), STI(STI) {
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 };
 
 /// RISCVOperand - Instances of this class represent a parsed machine
bool isUImm4() const {
     return (isConstantImm() && isUInt<4>(getConstantImm()));
   }
 
   bool isUImm5() const {
     return (isConstantImm() && isUInt<5>(getConstantImm()));
   }
 
   bool isSImm12() const {
-    return (isConstantImm() && isInt<12>(getConstantImm()));
+    if (isConstantImm()) {
+      return isInt<12>(getConstantImm());
+    } else if (isImm()) {
+      RISCVMCExpr::VariantKind VK;
+      int64_t Addend;
+      if (!RISCVAsmParser::classifySymbolRef(getImm(), VK, Addend))
+        return true;
+      return VK == RISCVMCExpr::VK_RISCV_LO;
+    }
+    return false;
   }
 
   bool isUImm12() const {
     return (isConstantImm() && isUInt<12>(getConstantImm()));
   }
 
   bool isSImm13Mask1() const {
     return (isConstantImm() && isInt<13>(getConstantImm()) &&
             getConstantImm() % 2 == 0);
   }
 
   bool isUImm20() const {
-    return (isConstantImm() && isUInt<20>(getConstantImm()));
+    if (isConstantImm()) {
+      return isUInt<20>(getConstantImm());
+    } else if (isImm()) {
+      RISCVMCExpr::VariantKind VK;
+      int64_t Addend;
+      if (!RISCVAsmParser::classifySymbolRef(getImm(), VK, Addend))
+        return true;
+      return VK == RISCVMCExpr::VK_RISCV_HI || VK == RISCVMCExpr::VK_RISCV_PCREL_HI;
+    }
+    return false;
   }
 
   bool isSImm21Mask1() const {
     return (isConstantImm() && isInt<21>(getConstantImm()) &&
             getConstantImm() % 2 == 0);
   }
 
   /// getStartLoc - Gets location of the first token of this operand
   SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Gets location of the last token of this operand
   SMLoc getEndLoc() const override { return EndLoc; }
 
   unsigned getReg() const override {
     assert(Kind == Register && "Invalid type access!");
     return Reg.RegNum;
   }
 
   const MCExpr *getImm() const {
     assert(Kind == Immediate && "Invalid type access!");
     return Imm.Val;
   }
 
   StringRef getToken() const {
     assert(Kind == Token && "Invalid type access!");
     return StringRef(Tok.Data, Tok.Length);
   }
 
   void print(raw_ostream &OS) const override {
static std::unique_ptr<RISCVOperand> createReg(unsigned RegNo, SMLoc S,
     auto Op = make_unique<RISCVOperand>(Register);
     Op->Reg.RegNum = RegNo;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
   static std::unique_ptr<RISCVOperand> createImm(const MCExpr *Val, SMLoc S,
-                                                 SMLoc E) {
+                                                 SMLoc E, MCContext &Ctx) {
     auto Op = make_unique<RISCVOperand>(Immediate);
+    if (const RISCVMCExpr *RE = dyn_cast<RISCVMCExpr>(Val)) {
+      int64_t Res;
+      if (RE->evaluateAsConstant(Res))
+        Val = MCConstantExpr::create(Res, Ctx);
+    }
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     assert(Expr && "Expr shouldn't be null!");
     if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
       Inst.addOperand(MCOperand::createImm(CE->getValue()));
     else
       Inst.addOperand(MCOperand::createExpr(Expr));
   }
 
   // Used by the TableGen Code
   void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
case AsmToken::Identifier:
     getLexer().Lex();
     Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
   return MatchOperand_Success;
 }
 
 RISCVAsmParser::OperandMatchResultTy
 RISCVAsmParser::parseImmediate(OperandVector &Operands) {
+  SMLoc S = Parser.getTok().getLoc();
+  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+  const MCExpr *Res;
+
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;
   case AsmToken::LParen:
   case AsmToken::Minus:
   case AsmToken::Plus:
   case AsmToken::Integer:
   case AsmToken::String:
+    if (getParser().parseExpression(Res))
+      return MatchOperand_ParseFail;
+    break;
+  case AsmToken::Identifier: {
+    StringRef Identifier;
+    if (getParser().parseIdentifier(Identifier))
+      return MatchOperand_ParseFail;
+    MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
+    Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+    break;
+  }
+  case AsmToken::Percent:
+    return parseOperandWithModifier(Operands);
     break;
   }
 
-  const MCExpr *IdVal;
+  Operands.push_back(RISCVOperand::createImm(Res, S, E, getContext()));
+  return MatchOperand_Success;
+}
+
+RISCVAsmParser::OperandMatchResultTy
+RISCVAsmParser::parseOperandWithModifier(OperandVector &Operands) {
   SMLoc S = Parser.getTok().getLoc();
-  if (getParser().parseExpression(IdVal))
+  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+  if (getLexer().getKind() != AsmToken::Percent) {
+    Error(getLoc(), "expected '%' for operand modifier");
     return MatchOperand_ParseFail;
+  }
 
-  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-  Operands.push_back(RISCVOperand::createImm(IdVal, S, E));
+  Parser.Lex(); // Eat '%'
+
+  if (getLexer().getKind() != AsmToken::Identifier) {
+    Error(getLoc(), "expected valid identifier for operand modifier");
+    return MatchOperand_ParseFail;
+  }
+  StringRef Identifier = Parser.getTok().getString();
+  RISCVMCExpr::VariantKind VK = RISCVMCExpr::getVariantKindForName(Identifier);
+  if (VK == RISCVMCExpr::VK_RISCV_None) {
+    Error(getLoc(), "unrecognized operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  Parser.Lex(); // Eat the identifier
+  if (getLexer().getKind() != AsmToken::LParen) {
+    Error(getLoc(), "expected '('");
+    return MatchOperand_ParseFail;
+  }
+  Parser.Lex(); // Eat '('
+
+  const MCExpr *SubExpr;
+  if (Parser.parseParenExpression(SubExpr, E)) {
+    return MatchOperand_ParseFail;
+  }
+
+  const MCExpr *ModExpr = RISCVMCExpr::create(SubExpr, VK, getContext());
+  Operands.push_back(RISCVOperand::createImm(ModExpr, S, E, getContext()));
   return MatchOperand_Success;
 }
 
 RISCVAsmParser::OperandMatchResultTy
 RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
   if (getLexer().getKind() != AsmToken::LParen) {
     Error(getLoc(), "expected '('");
     return MatchOperand_ParseFail;
   }
 
   Parser.Lex(); // Eat '('
   Operands.push_back(RISCVOperand::createToken("(", getLoc()));
 
   if (parseRegister(Operands) != MatchOperand_Success) {
     Error(getLoc(), "expected register");
     return MatchOperand_ParseFail;
   }
 
   if (getLexer().getKind() != AsmToken::RParen) {
     Error(getLoc(), "expected ')'");
     return MatchOperand_ParseFail;
   }
 
   Parser.Lex(); // Eat ')'
   Operands.push_back(RISCVOperand::createToken(")", getLoc()));
if (getLexer().isNot(AsmToken::EndOfStatement)) {
     Parser.eatToEndOfStatement();
     return Error(Loc, "unexpected token");
   }
 
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
+bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr,
+                                       RISCVMCExpr::VariantKind &Kind,
+                                       int64_t &Addend) {
+  Kind = RISCVMCExpr::VK_RISCV_Invalid;
+  Addend = 0;
+
+  if (const RISCVMCExpr *RE = dyn_cast<RISCVMCExpr>(Expr)) {
+    Kind = RE->getKind();
+    Expr = RE->getSubExpr();
+  }
+
+  assert(!isa<MCConstantExpr>(Expr) &&
+         "simple constants should have been evaluated already");
+
+  const MCSymbolRefExpr *SE = dyn_cast<MCSymbolRefExpr>(Expr);
+  if (SE) {
+    // It's a simple symbol reference with no addend.
+    return true;
+  }
+
+  const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr);
+  if (!BE)
+    return false;
+
+  SE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
+  if (!SE)
+    return false;
+
+  if (BE->getOpcode() != MCBinaryExpr::Add &&
+      BE->getOpcode() != MCBinaryExpr::Sub)
+    return false;
+
+  // See if the addend is is a constant, otherwise there's more going
+  // on here than we can deal with.
+  auto AddendExpr = dyn_cast<MCConstantExpr>(BE->getRHS());
+  if (!AddendExpr)
+    return false;
+
+  Addend = AddendExpr->getValue();
+  if (BE->getOpcode() == MCBinaryExpr::Sub)
+    Addend = -Addend;
+
+  // It's some symbol reference + a constant addend
+  return Kind != RISCVMCExpr::VK_RISCV_Invalid;
+}
+
 bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
 
 extern "C" void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(TheRISCV32Target);
   RegisterMCAsmParser<RISCVAsmParser> Y(TheRISCV64Target);
 }

lib/Target/RISCV/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMRISCVDesc
   RISCVAsmBackend.cpp
   RISCVELFObjectWriter.cpp
   RISCVMCAsmInfo.cpp
-  RISCVMCTargetDesc.cpp
   RISCVMCCodeEmitter.cpp
+  RISCVMCExpr.cpp
+  RISCVMCTargetDesc.cpp
 )

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "llvm/ADT/APInt.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCExpr.h"
public:
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
 
-  unsigned getNumFixupKinds() const override { return 1; }
+  unsigned getNumFixupKinds() const override {
+    return RISCV::NumTargetFixupKinds;
+  }
+
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
+    const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = {
+      // This table *must* be in the order that the fixup_* kinds are defined in
+      // RISCVFixupKinds.h.
+      //
+      // name                    offset bits  flags
+      { "fixup_riscv_hi20",       12,     20,  0 },
+      { "fixup_riscv_lo12_i",     20,     12,  0 },
+      { "fixup_riscv_lo12_s",      0,     32,  0 },
+      { "fixup_riscv_pcrel_hi20", 12,     20,  MCFixupKindInfo::FKF_IsPCRel }
+    };
+
+
+    if (Kind < FirstTargetFixupKind)
+      return MCAsmBackend::getFixupKindInfo(Kind);
+
+    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+           "Invalid kind!");
+    return Infos[Kind - FirstTargetFixupKind];
+  }
 
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
 
     llvm_unreachable("RISCVAsmBackend::relaxInstruction() unimplemented");
   }
bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
 
   // The canonical nop on RISC-V is addi x0, x0, 0
   for (uint64_t i = 0; i < Count; i += 4)
     OW->write32(0x13);
 
   return true;
 }
 
+static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("Unknown fixup kind!");
+  case FK_Data_1:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_Data_8:
+    return Value;
+  case RISCV::fixup_riscv_lo12_i:
+    return Value & 0xfff;
+  case RISCV::fixup_riscv_lo12_s:
+    return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
+  case RISCV::fixup_riscv_hi20:
+  case RISCV::fixup_riscv_pcrel_hi20:
+    // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
+    return ((Value + 0x800) >> 12) & 0xfffff;
+  }
+}
+
 void RISCVAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
                                  unsigned DataSize, uint64_t Value,
                                  bool IsPCRel) const {
+  MCFixupKind Kind = Fixup.getKind();
+  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
+  if (!Value)
+    return; // Doesn't change encoding.
+  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
+  // Apply any target-specific value adjustments.
+  Value = adjustFixupValue(Fixup.getKind(), Value);
+
+  // Shift the value into position.
+  Value <<= Info.TargetOffset;
+
+  unsigned Offset = Fixup.getOffset();
+  assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
+
+  // For each byte of the fragment that the fixup touches, mask in the
+  // bits from the fixup value.
+  for (unsigned i = 0; i != 4; ++i) {
+    unsigned Idx = i;
+    Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
+  }
   return;
 }
 
 MCObjectWriter *
 RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
   return createRISCVELFObjectWriter(OS, OSABI, Is64Bit);
 }
 

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

+//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone enum definitions for the RISCV target
+// useful for the compiler back-end and the MC libraries.
+//
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
+#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
+
+#include "RISCVMCTargetDesc.h"
+
+namespace llvm {
+
+// RISCVII - This namespace holds all of the target specific flags that
+// instruction info tracks. All definitions must match RISCVInstrFormats.td.
+namespace RISCVII {
+enum {
+  Pseudo = 0,
+  FrmR = 1,
+  FrmI = 2,
+  FrmS = 3,
+  FrmU = 4,
+  FrmOther = 5,
+
+  FormMask = 15
+};
+}
+}
+
+#endif

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 namespace {

 
 RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
 
 unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
                                             const MCValue &Target,
                                             const MCFixup &Fixup,
                                             bool IsPCRel) const {
   // Determine the type of the relocation
   switch ((unsigned)Fixup.getKind()) {
   default:
     llvm_unreachable("invalid fixup kind!");
+  case FK_Data_4:
+    return ELF::R_RISCV_32;
+  case FK_Data_8:
+    return ELF::R_RISCV_64;
+  case RISCV::fixup_riscv_hi20:
+    return ELF::R_RISCV_HI20;
+  case RISCV::fixup_riscv_lo12_i:
+    return ELF::R_RISCV_LO12_I;
+  case RISCV::fixup_riscv_lo12_s:
+    return ELF::R_RISCV_LO12_S;
+  case RISCV::fixup_riscv_pcrel_hi20:
+    return ELF::R_RISCV_PCREL_HI20;
   }
 }
 
 MCObjectWriter *llvm::createRISCVELFObjectWriter(raw_pwrite_stream &OS,
                                                  uint8_t OSABI, bool Is64Bit) {
   MCELFObjectTargetWriter *MOTW = new RISCVELFObjectWriter(OSABI, Is64Bit);
   return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
 }

lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

+//===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
+#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
+
+#include "llvm/MC/MCFixup.h"
+
+#undef RISCV
+
+namespace llvm {
+namespace RISCV {
+enum Fixups {
+  // fixup_riscv_hi20 - 20-bit fixup corresponding to hi(foo) for
+  // instructions like lui
+  fixup_riscv_hi20 = FirstTargetFixupKind,
+  // fixup_riscv_lo12_i - 12-bit fixup corresponding to lo(foo) for
+  // instructions like addi
+  fixup_riscv_lo12_i,
+  // fixup_riscv_lo12_s - 12-bit fixup corresponding to lo(foo) for
+  // the S-type store instructions
+  fixup_riscv_lo12_s,
+  // fixup_riscv_pcrel_hi20 - 20-bit fixup corresponding to pcrel_hi(foo) for
+  // instructions like auipc
+  fixup_riscv_pcrel_hi20,
+
+  // Marker
+  LastTargetFixupKind,
+  NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
+};
+} // end namespace RISCV
+} // end namespace llvm
+
+#endif

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the RISCVMCCodeEmitter class.
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/RISCVBaseInfo.h"
+#include "MCTargetDesc/RISCVFixupKinds.h"
+#include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/EndianStream.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mccodeemitter"
 
 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
+STATISTIC(MCNumFixups, "Number of MC fixups created.");
 
 namespace {
 class RISCVMCCodeEmitter : public MCCodeEmitter {
   RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
   void operator=(const RISCVMCCodeEmitter &) = delete;
   MCContext &Ctx;
+  MCInstrInfo const &MCII;
 
 public:
-  RISCVMCCodeEmitter(MCContext &ctx) : Ctx(ctx) {}
+  RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
+      : Ctx(ctx), MCII(MCII) {}
 
   ~RISCVMCCodeEmitter() override {}
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 
   /// TableGen'erated function for getting the binary encoding for an
   /// instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   /// Return binary encoding of operand. If the machine operand requires
   /// relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
+
   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
-  return new RISCVMCCodeEmitter(Ctx);
+  return new RISCVMCCodeEmitter(Ctx, MCII);
 }
 
 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
   support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
   const MCOperand &MO = MI.getOperand(OpNo);
 
   if (MO.isImm()) {
     unsigned Res = MO.getImm();
     assert((Res & 1) == 0 && "LSB is non-zero");
     return Res >> 1;
   }
 
-  llvm_unreachable("Unhandled expression!");
-
-  return 0;
+  return getImmOpValue(MI, OpNo, Fixups, STI);
 }
 
 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
 
   const MCOperand &MO = MI.getOperand(OpNo);
 
+  MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
+  unsigned MIFrm = Desc.TSFlags & RISCVII::FormMask;
+
   // If the destination is an immediate, there is nothing to do
   if (MO.isImm())
     return MO.getImm();
 
+  assert(MO.isExpr() &&
+         "getImmOpValue expects only expressions or immediates");
+  const MCExpr *Expr = MO.getExpr();
+  MCExpr::ExprKind Kind = Expr->getKind();
+  RISCV::Fixups FixupKind;
+  if (Kind == MCExpr::Target) {
+    const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
+
+    switch (RVExpr->getKind()) {
+    case RISCVMCExpr::VK_RISCV_None:
+    case RISCVMCExpr::VK_RISCV_Invalid:
+      llvm_unreachable("Unhandled fixup kind!");
+      break;
+    case RISCVMCExpr::VK_RISCV_LO:
+      FixupKind = MIFrm == RISCVII::FrmI ? RISCV::fixup_riscv_lo12_i
+                                         : RISCV::fixup_riscv_lo12_s;
+      break;
+    case RISCVMCExpr::VK_RISCV_HI:
+      FixupKind = RISCV::fixup_riscv_hi20;
+      break;
+    case RISCVMCExpr::VK_RISCV_PCREL_HI:
+      FixupKind = RISCV::fixup_riscv_pcrel_hi20;
+      break;
+    }
+  } else {
     llvm_unreachable("Unhandled expression!");
+  }
+  Fixups.push_back(
+      MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
+  ++MCNumFixups;
 
   return 0;
 }
 
 #include "RISCVGenMCCodeEmitter.inc"

lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h

+//===-- RISCVMCExpr.h - RISCV specific MC expression classes ----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes RISCV-specific MCExprs, used for modifiers like
+// "%hi" or "%lo" etc.,
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCEXPR_H
+#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCEXPR_H
+
+#include "llvm/MC/MCExpr.h"
+
+namespace llvm {
+
+class StringRef;
+class RISCVMCExpr : public MCTargetExpr {
+public:
+  enum VariantKind {
+    VK_RISCV_None,
+    VK_RISCV_LO,
+    VK_RISCV_HI,
+    VK_RISCV_PCREL_HI,
+    VK_RISCV_Invalid
+  };
+
+private:
+  const MCExpr *Expr;
+  const VariantKind Kind;
+
+  int64_t evaluateAsInt64(int64_t Value) const;
+
+  explicit RISCVMCExpr(const MCExpr *Expr, VariantKind Kind)
+      : Expr(Expr), Kind(Kind) {}
+
+public:
+  static const RISCVMCExpr *create(const MCExpr *Expr, VariantKind Kind,
+                                   MCContext &Ctx);
+
+  VariantKind getKind() const { return Kind; }
+
+  const MCExpr *getSubExpr() const { return Expr; }
+
+  void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
+  bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
+                                 const MCFixup *Fixup) const override;
+  void visitUsedExpr(MCStreamer &Streamer) const override;
+  MCFragment *findAssociatedFragment() const override {
+    return getSubExpr()->findAssociatedFragment();
+  }
+
+  // There are no TLS RISCVMCExprs at the moment.
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
+
+  bool evaluateAsConstant(int64_t &Res) const;
+
+  static bool classof(const MCExpr *E) {
+    return E->getKind() == MCExpr::Target;
+  }
+
+  static bool classof(const RISCVMCExpr *) { return true; }
+
+  static VariantKind getVariantKindForName(StringRef name);
+  static StringRef getVariantKindName(VariantKind Kind);
+};
+
+} // end namespace llvm.
+
+#endif

lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp

+//===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the implementation of the assembly expression modifiers
+// accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVMCExpr.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/ErrorHandling.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscvmcexpr"
+
+const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind,
+                                       MCContext &Ctx) {
+  return new (Ctx) RISCVMCExpr(Expr, Kind);
+}
+
+void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
+  bool HasVariant = getKind() != VK_RISCV_None;
+  if (HasVariant)
+    OS << '%' << getVariantKindName(getKind()) << '(';
+  Expr->print(OS, MAI);
+  if (HasVariant)
+    OS << ')';
+}
+
+bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
+                                            const MCAsmLayout *Layout,
+                                            const MCFixup *Fixup) const {
+  return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);
+}
+
+void RISCVMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
+  Streamer.visitUsedExpr(*getSubExpr());
+}
+
+RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) {
+  return StringSwitch<RISCVMCExpr::VariantKind>(name)
+      .Case("lo", VK_RISCV_LO)
+      .Case("hi", VK_RISCV_HI)
+      .Case("pcrel_hi", VK_RISCV_PCREL_HI)
+      .Default(VK_RISCV_None);
+}
+
+StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
+  switch (Kind) {
+  case VK_RISCV_LO:
+    return "lo";
+  case VK_RISCV_HI:
+    return "hi";
+  case VK_RISCV_PCREL_HI:
+    return "pcrel_hi";
+  default:
+    llvm_unreachable("Invalid ELF symbol kind");
+  }
+}
+
+bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
+  MCValue Value;
+
+  if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr))
+    return false;
+
+  if (!Value.isAbsolute())
+    return false;
+
+  Res = evaluateAsInt64(Value.getConstant());
+  return true;
+}
+
+int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const {
+  switch (Kind) {
+  case VK_RISCV_LO:
+    return SignExtend64<12>(Value);
+  case VK_RISCV_HI:
+    // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
+    return ((Value + 0x800) >> 12) & 0xfffff;
+  default:
+    llvm_unreachable("Invalid kind");
+  }
+}

lib/Target/RISCV/RISCVInstrFormats.td

 //  operations on the logical value represented. The immediate argument to
 //  these instruction formats instead represents the bit sequence that will be
 //  inserted into the instruction. e.g. although JAL's immediate is logically
 //  a 21-bit value (where the LSB is always zero), we describe it as an imm20
 //  to match how it is encoded.
 //
 //===----------------------------------------------------------------------===//
 
-class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern>
+// Format specifies the encoding used by the instruction. This is used by
+// RISCVMCCodeEmitter to determine which form of fixup to use. These
+// definitions must be kept in-sync with RISCVBaseInfo.h.
+class Format<bits<4> val> {
+  bits<4> Value = val;
+}
+def FrmPseudo : Format<0>;
+def FrmR      : Format<1>;
+def FrmI      : Format<2>;
+def FrmS      : Format<3>;
+def FrmU      : Format<4>;
+def FrmOther  : Format<5>;
+
+class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern, Format format>
     : Instruction {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
   // mainly used for ARM, but Tablegen expects this field to exist or it fails
   // to build the decode table.
   field bits<32> SoftFail = 0;
   let Size = 4;
 
   bits<7> Opcode = 0;
 
   let Inst{6-0} = Opcode;
 
   let Namespace = "RISCV";
 
   dag OutOperandList = outs;
   dag InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
+
+  let TSFlags{3-0} = format.Value;
 }
 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern> {
+    : RISCVInst<outs, ins, asmstr, pattern, FrmPseudo> {
   let isPseudo = 1;
 }
 
 class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
-         string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern>
+         string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern, FrmR>
 {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode;
 }
 
 class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmI>
 {
   bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-20} = imm12;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode;
 }
 
 class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmI>
 {
   bits<5> shamt;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31} = 0;
   let Inst{30} = arithshift;
   let Inst{29-25} = 0;
   let Inst{24-20} = shamt;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Opcode = opcode;
 }
 
 class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmS>
 {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31-25} = imm12{11-5};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = imm12{4-0};
   let Opcode = opcode;
 }
 
 class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmS>
 {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31} = imm12{11};
   let Inst{30-25} = imm12{9-4};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
   let Opcode = opcode;
 }
 
 class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmU>
 {
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
   let Opcode = opcode;
 }
 
 class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern>
+    : RISCVInst<outs, ins, asmstr, pattern, FrmU>
 {
   bits<21> imm20;
   bits<5> rd;
 
   let Inst{31} = imm20{19};
   let Inst{30-21} = imm20{9-0};
   let Inst{20} = imm20{10};
   let Inst{19-12} = imm20{18-11};
   let Inst{11-7} = rd;
   let Opcode = opcode;
 }

lib/Target/RISCV/RISCVInstrInfo.td

 
 def uimm5 : Operand<i32> {
   let ParserMatchClass = UImmAsmOperand<5>;
   let DecoderMethod = "decodeUImmOperand<5>";
 }
 
 def simm12 : Operand<i32> {
   let ParserMatchClass = SImmAsmOperand<12>;
+  let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<12>";
 }
 
 def uimm12 : Operand<i32> {
   let ParserMatchClass = UImmAsmOperand<12>;
   let DecoderMethod = "decodeUImmOperand<12>";
 }
 

 def SLT  : ALU_rr<0b0000000, 0b010, "slt">;
 def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
 def XOR  : ALU_rr<0b0000000, 0b100, "xor">;
 def SRL  : ALU_rr<0b0000000, 0b101, "srl">;
 def SRA  : ALU_rr<0b0100000, 0b101, "sra">;
 def OR   : ALU_rr<0b0000000, 0b110, "or">;
 def AND  : ALU_rr<0b0000000, 0b111, "and">;
 
-def FENCE : RISCVInst<(outs), (ins uimm4:$pred, uimm4:$succ), "fence\t$pred, $succ", []>
+def FENCE : RISCVInst<(outs), (ins uimm4:$pred, uimm4:$succ), "fence\t$pred, $succ", [], FrmOther>
 {
   bits<4> pred;
   bits<4> succ;
 
   let Opcode = 0b0001111;
   let Inst{19-7} = 0;
   let Inst{23-20} = succ;
   let Inst{27-24} = pred;
   let Inst{31-28} = 0;
 }
 
-def FENCEI : RISCVInst<(outs), (ins), "fence.i", []> {
+def FENCEI : RISCVInst<(outs), (ins), "fence.i", [], FrmOther> {
   let Opcode = 0b0001111;
   let Inst{11-7} = 0;
   let Inst{14-12} = 0b001;
   let Inst{31-15} = 0;
 }
 
 let rs1=0, rd=0 in {
   def ECALL  : FI<0b000, 0b1110011, (outs), (ins), "ecall", []> {

test/MC/RISCV/fixups.s

+# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN:     | FileCheck -check-prefix=CHECK-FIXUP %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INSTR %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
+# RUN:     | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
+
+# Checks that fixups that can be resolved within the same object file are 
+# applied correctly
+
+lui t1, %hi(val)
+# CHECK-FIXUP: fixup A - offset: 0, value: %hi(val), kind: fixup_riscv_hi20
+# CHECK-INSTR: lui t1, 74565
+
+lw a0, %lo(val)(t1)
+# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
+# CHECK-INSTR: lw a0, 1656(t1)
+addi a1, t1, %lo(val)
+# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
+# CHECK-INSTR: addi a1, t1, 1656
+sw a0, %lo(val)(t1)
+# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_s
+# CHECK-INSTR: sw a0, 1656(t1)
+
+.set val, 0x12345678
+
+# CHECK-REL-NOT: R_RISCV

test/MC/RISCV/hilo-constaddr.s

+# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
+# RUN:  | llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-INSTR
+
+# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
+# RUN:  | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
+
+# Check the assembler can handle hi and lo expressions with a constant 
+# address, and constant expressions involving labels. Test case derived from 
+# test/MC/Mips/hilo-addressing.s
+
+# Check that 1 is added to the high 20 bits if bit 11 of the low part is 1.
+.equ addr, 0xdeadbeef
+  lui t0, %hi(addr)
+  lw ra, %lo(addr)(t0)
+# CHECK-INSTR: lui t0, 912092
+# CHECK-INSTR: lw ra, -273(t0)
+
+# Check that assembler can handle %hi(label1 - label2) and %lo(label1 - label2)
+# expressions.
+
+tmp1:
+  # Emit zeros so that difference between tmp1 and tmp3 is 0x30124 bytes.
+  .fill 0x30124-8
+tmp2:
+  lui t0, %hi(tmp3-tmp1)
+  lw ra, %lo(tmp3-tmp1)(t0)
+# CHECK-INSTR: lui t0, 48
+# CHECK-INSTR: lw ra, 292(t0)
+
+tmp3:
+  lui t1, %hi(tmp2-tmp3)
+  lw sp, %lo(tmp2-tmp3)(t1)
+# CHECK-INSTR: lui t1, 0
+# CHECK-INSTR: lw sp, -8(t1)
+
+# Check that a relocation isn't emitted for %hi(label1 - label2) and
+# %lo(label1 - label2) expressions.
+
+# CHECK-REL-NOT: R_RISCV

test/MC/RISCV/relocations.s

+# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN:     | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+
+# Check prefixes:
+# RELOC - Check the relocation in the object.
+# FIXUP - Check the fixup on the instruction.
+# INSTR - Check the instruction is handled properly by the ASMPrinter
+
+.long foo
+# RELOC: R_RISCV_32 foo
+
+.quad foo
+# RELOC: R_RISCV_64 foo
+
+lui t1, %hi(foo)
+# RELOC: R_RISCV_HI20 foo
+# INSTR: lui t1, %hi(foo)
+# FIXUP: fixup A - offset: 0, value: %hi(foo), kind: fixup_riscv_hi20
+
+addi t1, t1, %lo(foo)
+# RELOC: R_RISCV_LO12_I foo
+# INSTR: addi t1, t1, %lo(foo)
+# FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_i
+
+sb t1, %lo(foo)(a2)
+# RELOC: R_RISCV_LO12_S foo
+# INSTR: sb t1, %lo(foo)(a2)
+# FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_s
+
+auipc t1, %pcrel_hi(foo)
+# RELOC: R_RISCV_PCREL_HI20
+# INSTR: auipc t1, %pcrel_hi(foo)
+# FIXUP: fixup A - offset: 0, value: %pcrel_hi(foo), kind: fixup_riscv_pcrel_hi20

test/MC/RISCV/rv32i-invalid.s

 csrrsi a0, 4097, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
 csrrci a0, 0xffff, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
 
 # Invalid mnemonics
 subs t0, t2, t1 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
 nandi t0, zero, 0 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
 
 # Invalid register names
-addi foo, sp, 10 # CHECK: :[[@LINE]]:6: error: unknown operand
-slti a10, a2, 0x20 # CHECK: :[[@LINE]]:6: error: unknown operand
-slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: unknown operand
+addi foo, sp, 10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+slti a10, a2, 0x20 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 
 # RV64I mnemonics
 addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
 sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
 
 # Invalid operand types
 xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 
 # Too many operands
 add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
 sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
 
 # Too few operands
 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

test/MC/RISCV/rv32i-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -show-encoding | FileCheck %s
 # RUN: llvm-mc %s -triple=riscv64 -show-encoding | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-DIS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-DIS %s
 
 lui a0, 2 # CHECK: encoding: [0x37,0x25,0x00,0x00]
 # CHECK-DIS: lui a0, 2
+lui a0, %hi(2) # CHECK: encoding: [0x37,0x05,0x00,0x00]
+# CHECK-DIS: lui a0, 0
 lui s11, (0x87000000>>12) # CHECK: encoding: [0xb7,0x0d,0x00,0x87]
 # CHECK-DIS: lui s11, 552960
+lui s11, %hi(0x87000000) # CHECK: encoding: [0xb7,0x0d,0x00,0x87]
+# CHECK-DIS: lui s11, 552960
 lui t0, 1048575 # CHECK: encoding: [0xb7,0xf2,0xff,0xff]
 # CHECK-DIS: lui t0, 1048575
 lui gp, 0 # CHECK: encoding: [0xb7,0x01,0x00,0x00]
 # CHECK-DIS: lui gp, 0
 
 auipc a0, 2 # CHECK: encoding: [0x17,0x25,0x00,0x00]
 # CHECK-DIS: auipc a0, 2
 auipc s11, (0x87000000>>12) # CHECK: encoding: [0x97,0x0d,0x00,0x87]
 # CHECK-DIS: auipc s11, 552960
 auipc t0, 1048575 # CHECK: encoding: [0x97,0xf2,0xff,0xff]
 # CHECK-DIS: auipc t0, 1048575
 auipc gp, 0 # CHECK: encoding: [0x97,0x01,0x00,0x00]
 # CHECK-DIS: auipc gp, 0
 
 jal a2, 1048574 # CHECK: encoding: [0x6f,0xf6,0xff,0x7f]
 # CHECK-DIS: jal a2, 1048574
 jal a3, 256 # CHECK: encoding: [0xef,0x06,0x00,0x10]
 # CHECK-DIS: jal a3, 256
 
 jalr a0, a1, -2048 # CHECK: encoding: [0x67,0x85,0x05,0x80]
 # CHECK-DIS: jalr a0, a1, -2048
+jalr a0, a1, %lo(2048) # CHECK: encoding: [0x67,0x85,0x05,0x80]
+# CHECK-DIS: jalr a0, a1, -2048
 jalr t2, t1, 2047 # CHECK: encoding: [0xe7,0x03,0xf3,0x7f]
 # CHECK-DIS: jalr t2, t1, 2047
 jalr sp, zero, 256 # CHECK: encoding: [0x67,0x01,0x00,0x10]
 # CHECK-DIS: jalr sp, zero, 256
 
 beq s1, s1, 102 # CHECK: encoding: [0x63,0x83,0x94,0x06]
 # CHECK-DIS: beq s1, s1, 102
 bne a4, a5, -4096 # CHECK: encoding: [0x63,0x10,0xf7,0x80]

 
 
 lb s3, 4(ra) # CHECK: encoding: [0x83,0x89,0x40,0x00]
 # CHECK-DIS: lb s3, 4(ra)
 lb s3, +4(ra) # CHECK: encoding: [0x83,0x89,0x40,0x00]
 # CHECK-DIS: lb s3, 4(ra)
 lh t1, -2048(zero) # CHECK: encoding: [0x03,0x13,0x00,0x80]
 # CHECK-DIS: lh t1, -2048(zero)
+lh t1, %lo(2048)(zero) # CHECK: encoding: [0x03,0x13,0x00,0x80]
+# CHECK-DIS: lh t1, -2048(zero)
 lh sp, 2047(a0) # CHECK: encoding: [0x03,0x11,0xf5,0x7f]
 # CHECK-DIS: lh sp, 2047(a0)
 lw a0, 97(a2) # CHECK: encoding: [0x03,0x25,0x16,0x06]
 # CHECK-DIS: lw a0, 97(a2)
 lbu s5, 0(s6) # CHECK: encoding: [0x83,0x4a,0x0b,0x00]
 # CHECK-DIS: lbu s5, 0(s6)
 lhu t3, 255(t3) # CHECK: encoding: [0x03,0x5e,0xfe,0x0f]
 # CHECK-DIS: lhu t3, 255(t3)
 
 sb a0, 2047(a2) # CHECK: encoding: [0xa3,0x0f,0xa6,0x7e]
 # CHECK-DIS: sb a0, 2047(a2)
 sh t3, -2048(t5) # CHECK: encoding: [0x23,0x10,0xcf,0x81]
 # CHECK-DIS: sh t3, -2048(t5)
+sh t3, %lo(2048)(t5) # CHECK: encoding: [0x23,0x10,0xcf,0x81]
+# CHECK-DIS: sh t3, -2048(t5)
 sw ra, 999(zero) # CHECK: encoding: [0xa3,0x23,0x10,0x3e]
 # CHECK-DIS: sw ra, 999(zero)
 
 addi ra, sp, 2 # CHECK: encoding: [0x93,0x00,0x21,0x00]
 # CHECK-DIS: addi ra, sp, 2
 slti a0, a2, -20 # CHECK: encoding: [0x13,0x25,0xc6,0xfe]
 # CHECK-DIS: slti a0, a2, -20
 sltiu s2, s3, 0x50 # CHECK: encoding: [0x13,0xb9,0x09,0x05]
 # CHECK-DIS: sltiu s2, s3, 80
 xori tp, t1, -99 # CHECK: encoding: [0x13,0x42,0xd3,0xf9]
 # CHECK-DIS: xori tp, t1, -99
 ori a0, a1, -2048 # CHECK: encoding: [0x13,0xe5,0x05,0x80]
 # CHECK-DIS: ori a0, a1, -2048
+ori a0, a1, %lo(2048) # CHECK: encoding: [0x13,0xe5,0x05,0x80]
+# CHECK-DIS: ori a0, a1, -2048
 andi ra, sp, 2047 # CHECK: encoding: [0x93,0x70,0xf1,0x7f]
 # CHECK-DIS: andi ra, sp, 2047
 andi x1, x2, 2047 # CHECK: encoding: [0x93,0x70,0xf1,0x7f]
 # CHECK-DIS: andi ra, sp, 2047
 
 slli t3, t3, 31 # CHECK: encoding: [0x13,0x1e,0xfe,0x01]
 # CHECK-DIS: slli t3, t3, 31
 srli a0, a4, 0 # CHECK: encoding: [0x13,0x55,0x07,0x00]