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[RISCV] Add common fixups and relocations

Description

[RISCV] Add common fixups and relocations

%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to
ensure the appropriate fixups and relocations are generated. I've added an
instruction format field which is used in RISCVMCCodeEmitter to, for
instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup
(RISC-V has two 12-bit immediate encodings depending on the instruction
type).

Differential Revision: https://reviews.llvm.org/D23568

Details

Committed
asbSep 28 2017, 1:26 AM
Differential Revision
D23568: [RISCV 10/10] Add common fixups and relocations
Parents
rL314388: [RegAllocGreedy]: Allow recoloring of done register if it's non-tied
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