Don't ignore MCTargetOptions::ABIName on targets that currently do so.

[sdardis]

Summary

This makes these targets consistent with ARM/PowerPC in that they
technically accept ABI information via MCTargetOptions::ABIName but they
only implement one ABI (the empty string).

AArch64 is slightly special in that it also accepts "aapcs" and "darwinpcs"
in addition to the empty string. These names are only used in Clang and
have no functional effect on the backend.

X86 is somewhat special in that it's the only target that supports multiple
ABI's but only accepts the empty string. I can define "32", "x32", and "64"
if that's desirable but it's not necessary for functionality.

No corresponding change is required to clang because targets that don't pass
-target-abi get the empty string by default and those that need to pass it
already do so.

Depends on D21069

[dsanders]

Before this patch, the camps were:

• Targets that pass ABI information in both the triple and MCTargetOptions (ARM/PowerPC)
• Targets that pass ABI information in the triple only (Mips/X86/everyone-else)

At this point the camps are:

• Targets that pass ABI information in both the triple and MCTargetOptions (ARM/PowerPC/X86/everyone-else)
  • As noted in the description, X86 is in this camp on a technicality. Let me know if you want me to do more to X86
• Targets that pass ABI information in the triple only (Mips)

The next two patches (one clang, one llvm) should finish the unification of the two camps.

[dsanders]

Refresh and ping

[dsanders]

Refresh and ping

[dsanders]

One last ping since I need to either commit this series next week or hand over to a colleague to continue it.

[sdardis]

Taking over this patch series.

[sdardis]

Rebase + ping. I am aware that you're exploring your alternate solution Eric.

[sdardis]

Rebase and ping.

[sdardis]

Ping.

[sdardis]

Ping.

[sdardis]

Rebase and ping

lib/Target/AArch64/AArch64TargetMachine.cpp

AArch64TargetMachine::AArch64TargetMachine(
     // This nested ternary is horrible, but DL needs to be properly
     // initialized before TLInfo is constructed.
     : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
                                              LittleEndian),
                         TT, CPU, FS, Options,
       getEffectiveRelocModel(TT, RM), CM, OL),
       TLOF(createTLOF(getTargetTriple())),
       isLittle(LittleEndian) {
+  assert((Options.MCOptions.ABIName.empty() ||
+          Options.MCOptions.ABIName == "aapcs" ||
+          Options.MCOptions.ABIName == "darwinpcs" ||
+          Options.MCOptions.ABIName == "ilp32") &&
+         "Unexpected ABI");
   initAsmInfo();
 }
 
 AArch64TargetMachine::~AArch64TargetMachine() {}
 
 #ifdef LLVM_BUILD_GLOBAL_ISEL
 namespace {
 struct AArch64GISelActualAccessor : public GISelAccessor {

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
                                          TargetOptions Options,
                                          Optional<Reloc::Model> RM,
                                          CodeModel::Model CM,
                                          CodeGenOpt::Level OptLevel)
   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
     TLOF(createTLOF(getTargetTriple())),
     IntrinsicInfo() {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   setRequiresStructuredCFG(true);
   initAsmInfo();
 }
 
 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
 
 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
   Attribute GPUAttr = F.getFnAttribute("target-cpu");

lib/Target/AVR/AVRTargetMachine.cpp

AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM, CodeModel::Model CM,
                                    CodeGenOpt::Level OL)
     : LLVMTargetMachine(
           T, AVRDataLayout, TT,
           getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL),
       SubTarget(TT, getCPU(CPU), FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   this->TLOF = make_unique<AVRTargetObjectFile>();
   initAsmInfo();
 }
 
 namespace {
 /// AVR Code Generator Pass Configuration Options.
 class AVRPassConfig : public TargetPassConfig {
 public:

lib/Target/BPF/BPFTargetMachine.cpp

BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    CodeModel::Model CM, CodeGenOpt::Level OL)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM), CM, OL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 namespace {
 // BPF Code Generator Pass Configuration Options.
 class BPFPassConfig : public TargetPassConfig {
 public:
   BPFPassConfig(BPFTargetMachine *TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}

lib/Target/Hexagon/HexagonTargetMachine.cpp

HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
     // the required minimum of 64 bytes.
     : LLVMTargetMachine(
           T, "e-m:e-p:32:32:32-a:0-n16:32-"
              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
           (HexagonNoOpt ? CodeGenOpt::None : OL)),
       TLOF(make_unique<HexagonTargetObjectFile>()) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
   initAsmInfo();
 }
 
 const HexagonSubtarget *
 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
   AttributeSet FnAttrs = F.getAttributes();
   Attribute CPUAttr =

lib/Target/Lanai/LanaiTargetMachine.cpp

LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        CodeModel::Model CodeModel,
                                        CodeGenOpt::Level OptLevel)
     : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
                         getEffectiveRelocModel(RM), CodeModel, OptLevel),
       Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel),
       TLOF(new LanaiTargetObjectFile()) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 
 TargetIRAnalysis LanaiTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(LanaiTTIImpl(this, F));
   });
 }

lib/Target/MSP430/MSP430TargetMachine.cpp

MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
                                          Optional<Reloc::Model> RM,
                                          CodeModel::Model CM,
                                          CodeGenOpt::Level OL)
     : LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS,
                         Options, getEffectiveRelocModel(RM), CM, OL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       // FIXME: Check DataLayout string.
       Subtarget(TT, CPU, FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 
 MSP430TargetMachine::~MSP430TargetMachine() {}
 
 namespace {
 /// MSP430 Code Generator Pass Configuration Options.
 class MSP430PassConfig : public TargetPassConfig {

lib/Target/NVPTX/NVPTXTargetMachine.cpp

NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
                                        CodeGenOpt::Level OL, bool is64bit)
     // The pic relocation model is used regardless of what the client has
     // specified, as it is the only relocation model currently supported.
     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
                         Reloc::PIC_, CM, OL),
       is64bit(is64bit),
       TLOF(make_unique<NVPTXTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   if (TT.getOS() == Triple::NVCL)
     drvInterface = NVPTX::NVCL;
   else
     drvInterface = NVPTX::CUDA;
   initAsmInfo();
 }
 
 NVPTXTargetMachine::~NVPTXTargetMachine() {}

lib/Target/Sparc/SparcTargetMachine.cpp

SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        CodeModel::Model CM,
                                        CodeGenOpt::Level OL, bool is64bit)
     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM), CM, OL),
       TLOF(make_unique<SparcELFTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 
 SparcTargetMachine::~SparcTargetMachine() {}
 
 const SparcSubtarget * 
 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");

lib/Target/SystemZ/SystemZTargetMachine.cpp

SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            CodeModel::Model CM,
                                            CodeGenOpt::Level OL)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM), CM, OL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 
 SystemZTargetMachine::~SystemZTargetMachine() {}
 
 namespace {
 /// SystemZ Code Generator Pass Configuration Options.
 class SystemZPassConfig : public TargetPassConfig {

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

WebAssemblyTargetMachine::WebAssemblyTargetMachine(
     const TargetOptions &Options, Optional<Reloc::Model> RM,
     CodeModel::Model CM, CodeGenOpt::Level OL)
     : LLVMTargetMachine(T,
                         TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
                                          : "e-m:e-p:32:32-i64:64-n32:64-S128",
                         TT, CPU, FS, Options, getEffectiveRelocModel(RM),
                         CM, OL),
       TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
+
   // WebAssembly type-checks instructions, but a noreturn function with a return
   // type that doesn't match the context will cause a check failure. So we lower
   // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
   // 'unreachable' instructions which is meant for that case.
   this->Options.TrapUnreachable = true;
 
   initAsmInfo();
 

lib/Target/X86/X86TargetMachine.cpp

 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    CodeModel::Model CM, CodeGenOpt::Level OL)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM), CM, OL),
       TLOF(createTLOF(getTargetTriple())) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
+
   // Windows stack unwinder gets confused when execution flow "falls through"
   // after a call to 'noreturn' function.
   // To prevent that, we emit a trap for 'unreachable' IR instructions.
   // (which on X86, happens to be the 'ud2' instruction)
   // On PS4, the "return address" of a 'noreturn' call must still be within
   // the calling function, and TrapUnreachable is an easy way to get that.
   // The check here for 64-bit windows is a bit icky, but as we're unlikely
   // to ever want to mix 32 and 64-bit windows code in a single module

lib/Target/XCore/XCoreTargetMachine.cpp

XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
                                        Optional<Reloc::Model> RM,
                                        CodeModel::Model CM,
                                        CodeGenOpt::Level OL)
     : LLVMTargetMachine(
           T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
       TLOF(make_unique<XCoreTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
+  assert(Options.MCOptions.ABIName.empty() && "Unexpected ABI");
   initAsmInfo();
 }
 
 XCoreTargetMachine::~XCoreTargetMachine() {}
 
 namespace {
 /// XCore Code Generator Pass Configuration Options.
 class XCorePassConfig : public TargetPassConfig {