[RISCV] Don't add -unaligned-scalar-mem to target features by default.

[craig.topper]

Summary

Only pass it +unaligned-scalar-mem/-unaligned-scalar-mem if the
user has passed one of the alignment options.

This allows us to add unaligned-scalar-mem as a feature on CPUs
that support it.

[wangpc]

llvm/lib/Target/RISCV/RISCVProcessors.td

185

This can be tested in clang/test/Driver/riscv-cpus.c.

[craig.topper]

llvm/lib/Target/RISCV/RISCVProcessors.td

185

This shouldn’t be in here. That was for testing and I accidentally committed it

[wangpc]

llvm/lib/Target/RISCV/RISCVProcessors.td

185

Are there any processors in upstream that support unaligned memory access so that we can test it?

[craig.topper]

Remove change to sifive-x280.

[wangpc]

LGTM.

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   // specified.
   if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false))
     Features.push_back("+save-restore");
   else
     Features.push_back("-save-restore");
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
   bool HasV = llvm::is_contained(Features, "+zve32x");
-  if (Args.hasFlag(options::OPT_munaligned_access,
-                   options::OPT_mno_unaligned_access, false)) {
+  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
+                                     options::OPT_mno_unaligned_access)) {
+    if (A->getOption().matches(options::OPT_munaligned_access)) {
       Features.push_back("+unaligned-scalar-mem");
       if (HasV)
         Features.push_back("+unaligned-vector-mem");
     } else {
       Features.push_back("-unaligned-scalar-mem");
       if (HasV)
         Features.push_back("-unaligned-vector-mem");
     }
+  }
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,
                             options::OPT_m_riscv_Features_Group);
 }
 
 StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {

clang/test/Driver/riscv-default-features.c

 // RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
 // RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
-// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
-// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
   return  3;
 }

clang/test/Driver/riscv-features.c

 // RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
 // RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
 // RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
 
 // UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
 // NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
 // UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
 // NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
-// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
-// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
 // RUN: %clang --target=riscv64-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
 
 // DEFAULT-LINUX: "-funwind-tables=2"
 // DEFAULT-LINUX-SAME: "-target-feature" "+m"

llvm/lib/Target/RISCV/RISCVProcessors.td

def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
                                        FeatureStdExtF,
                                        FeatureStdExtD,
                                        FeatureStdExtC,
                                        FeatureStdExtV,
                                        FeatureStdExtZvl512b,
                                        FeatureStdExtZfh,
                                        FeatureStdExtZvfh,
                                        FeatureStdExtZba,
-                                       FeatureStdExtZbb],
+                                       FeatureStdExtZbb,
+                                       FeatureUnalignedScalarMem],
                                       [TuneSiFive7,
                                        TuneDLenFactor2]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,
                                               [Feature32Bit,
                                                FeatureStdExtZicsr,
                                                FeatureStdExtZifencei,