This patch adds a helper to check if the tail loop is folded in a
VPlan.
To do so it checks if the VPlan contains a widen canonical IV, a
active-lane-mask-phi, an active-lane-mask or a ICmpULE compare of a
widened canonical induction with the backedge taken count. This should
effectively check if a mask for the header is present, but may be a bit
cumbersome.
Alternatively we could also add a flag to the VPlan.
Depends on D157037.
Could recipes be set initially such that they generate code as needed, rather than (figuring out if tail was folded in order to) fix it here? This seems to require (a) setting FMF of Sel's recipe, (b) optionally rewiring a header phi recipe to Sel's recipe, (c) RAUW of LoopExitInstDef with Sel's recipe, rather than State.reset().