Please use GitHub pull requests for new patches. Phabricator shutdown timeline

[RISCV] Add CFI information for vector callee-saved registers
Needs ReviewPublic
Actions

Authored by 4vtomat on Aug 1 2023, 7:48 PM.

Details

Reviewers

asb
craig.topper
kito.cheng

Summary

Currently the CFI offset for RVV registers are not handled entirely,
this patch add those information for either stack unwinding or
debugger to work correctly on RVV callee-saved stack object.

Depends On D154576

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

4vtomat created this revision.Aug 1 2023, 7:48 PM

Herald added a project: Restricted Project. · View Herald TranscriptAug 1 2023, 7:48 PM

Herald added subscribers: jobnoorman, luke, VincentWu and 33 others. · View Herald Transcript

4vtomat requested review of this revision.Aug 1 2023, 7:48 PM

Herald added a project: Restricted Project. · View Herald TranscriptAug 1 2023, 7:48 PM

Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript

Harbormaster completed remote builds in B249657: Diff 546299.Aug 1 2023, 7:49 PM

4vtomat added reviewers: asb, craig.topper, kito.cheng.Aug 1 2023, 7:51 PM

Revision Contents
Changeset List

Path

Size

llvm/

lib/

Target/

RISCV/

RISCVFrameLowering.h

5 lines

RISCVFrameLowering.cpp

144 lines

test/

CodeGen/

RISCV/

early-clobber-tied-def-subreg-liveness.ll

1 line

regalloc-last-chance-recoloring-failure.ll

2 lines

rvv-cfi-info.ll

225 lines

rvv/

abs-vp.ll

1 line

access-fixed-objects-by-rvv.ll

1 line

addi-scalable-offset.mir

1 line

alloca-load-store-scalable-struct.ll

1 line

1 line

8 lines

1 line

7 lines

calling-conv-fastcc.ll

8 lines

2 lines

1 line

1 line

3 lines

4 lines

1 line

4 lines

extractelt-int-rv32.ll

2 lines

extractelt-int-rv64.ll

2 lines

fixed-vectors-bitreverse-vp.ll

8 lines

fixed-vectors-bswap-vp.ll

7 lines

fixed-vectors-ceil-vp.ll

1 line

fixed-vectors-ctlz-vp.ll

6 lines

fixed-vectors-ctpop-vp.ll

3 lines

fixed-vectors-cttz-vp.ll

6 lines

fixed-vectors-floor-vp.ll

1 line

fixed-vectors-fp-interleave.ll

2 lines

fixed-vectors-fshr-fshl-vp.ll

4 lines

fixed-vectors-insert-subvector.ll

2 lines

fixed-vectors-int-interleave.ll

2 lines

fixed-vectors-interleaved-access.ll

2 lines

fixed-vectors-reduction-int.ll

4 lines

fixed-vectors-rint-vp.ll

1 line

fixed-vectors-round-vp.ll

1 line

fixed-vectors-roundeven-vp.ll

1 line

fixed-vectors-roundtozero-vp.ll

1 line

fixed-vectors-setcc-fp-vp.ll

2 lines

fixed-vectors-setcc-int-vp.ll

2 lines

fixed-vectors-trunc-vp.ll

1 line

fixed-vectors-vcopysign-vp.ll

1 line

fixed-vectors-vfma-vp.ll

2 lines

fixed-vectors-vfmax-vp.ll

1 line

fixed-vectors-vfmin-vp.ll

1 line

fixed-vectors-vfmuladd-vp.ll

2 lines

fixed-vectors-vfwadd.ll

2 lines

fixed-vectors-vfwmul.ll

2 lines

fixed-vectors-vfwsub.ll

2 lines

fixed-vectors-vpgather.ll

1 line

fixed-vectors-vpmerge.ll

1 line

fixed-vectors-vpscatter.ll

4 lines

fixed-vectors-vscale-range.ll

1 line

fixed-vectors-vselect-vp.ll

5 lines

fixed-vectors-vwmul.ll

3 lines

fixed-vectors-vwmulsu.ll

3 lines

fixed-vectors-vwmulu.ll

3 lines

floor-vp.ll

1 line

fpclamptosat_vec.ll

24 lines

fshr-fshl-vp.ll

12 lines

get-vlen-debugloc.mir

1 line

large-rvv-stack-size.mir

1 line

8 lines

1 line

1 line

1 line

named-vector-shuffle-reverse.ll

6 lines

no-reserved-frame.ll

1 line

reg-alloc-reserve-bp.ll

1 line

1 line

1 line

1 line

1 line

1 line

2 lines

2 lines

2 lines

vector-deinterleave-load.ll

1 line

vector-deinterleave.ll

3 lines

vector-interleave-store.ll

1 line

2 lines

2 lines

2 lines

2 lines

1 line

3 lines

1 line

1 line

3 lines

1 line

1 line

Diff 546299

View Options

llvm/lib/Target/RISCV/RISCVFrameLowering.h

View Options

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

View Options

llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

View Options

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

View Options

llvm/test/CodeGen/RISCV/rvv-cfi-info.ll

View Options

llvm/test/CodeGen/RISCV/rvv/abs-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

View Options

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

View Options

llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll

View Options

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

View Options

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

View Options

llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

View Options

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

View Options

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

View Options

llvm/test/CodeGen/RISCV/rvv/floor-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

View Options

llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

View Options

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

View Options

llvm/test/CodeGen/RISCV/rvv/localvar.ll

View Options

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

View Options

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

View Options

llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

View Options

llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/rint-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/round-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll

View Options

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vpstore.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

View Options

llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

[RISCV] Add CFI information for vector callee-saved registersNeeds ReviewPublicActions

Details

Diff Detail

Event Timeline

Revision ContentsChangeset List

Diff 546299

llvm/lib/Target/RISCV/RISCVFrameLowering.h

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

llvm/test/CodeGen/RISCV/rvv-cfi-info.ll

llvm/test/CodeGen/RISCV/rvv/abs-vp.ll

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll

llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/floor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

llvm/test/CodeGen/RISCV/rvv/localvar.ll

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll

llvm/test/CodeGen/RISCV/rvv/rint-vp.ll

llvm/test/CodeGen/RISCV/rvv/round-vp.ll

[RISCV] Add CFI information for vector callee-saved registers
Needs ReviewPublic
Actions

Revision Contents
Changeset List